SC68C2550B データシートの表示（PDF） - NXP Semiconductors.

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SC68C2550B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs and 68 mode µP interface

NXP Semiconductors. 

NXP Semiconductors

SC68C2550B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

6.2 Internal registers

The SC68C2550B provides two sets of internal registers (A and B) consisting of

12 registers each for monitoring and controlling the functions of each channel of the

UART. These registers are shown in Table 4. The UART registers function as data holding

registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control

register (FCR), line status and control registers (LCR/LSR), modem status and control

registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a

user accessible scratchpad register (SPR).

Table 4. Internal registers decoding

A2 A1 A0 Read mode

Write mode

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, SPR)[1]

0

0

0

Receive Holding Register

Transmit Holding Register

0

0

1

Interrupt Enable Register

Interrupt Enable Register

0

1

0

Interrupt Status Register

FIFO Control Register

0

1

1

Line Control Register

Line Control Register

1

0

0

Modem Control Register

Modem Control Register

1

0

1

Line Status Register

n/a

1

1

0

Modem Status Register

n/a

1

1

1

Scratchpad Register

Scratchpad Register

Baud rate register set (DLL/DLM)[2]

0

0

0

LSB of Divisor Latch

LSB of Divisor Latch

0

0

1

MSB of Divisor Latch

MSB of Divisor Latch

[1] These registers are accessible only when LCR[7] is a logic 0.

[2] These registers are accessible only when LCR[7] is a logic 1.

6.3 FIFO operation

The 16 byte transmit and receive data FIFOs are enabled by the FIFO Control Register

(FCR) bit 0. The user can set the receive trigger level via FCR[7:6], but not the transmit

trigger level. The receiver FIFO section includes a time-out function to ensure data is

delivered to the external CPU. An interrupt is generated whenever the Receive Holding

Register (RHR) has not been read following the loading of a character or the receive

trigger level has not been reached.

Table 5. Flow control mechanism

Selected trigger level (characters)

1

4

8

14

IRQ pin activation

1

4

8

14

SC68C2550B_3

Product data sheet

Rev. 03 — 9 October 2009

© NXP B.V. 2009. All rights reserved.

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