SC905 データシートの表示（PDF） - Semtech Corporation
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SC905 Datasheet PDF : 21 Pages
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SC905
POWER MANAGEMENT
Using the I2C Serial Port
I2C Direct Format - Write
S Slave Address W A Register Address A
Data
AP
S: Start Condition
W: Write = ‘0’
A: Acknowledge (sent by slave)
P: Stop condition
Slave Address: 7 bit
Register Address: 8 bit
Data: 8 bit
Combined Format - Read
After the start condition [S], the slave address is sent, followed by an eighth bit indicating a write. The SC905 I2C then
acknowledges that it is being addressed, and the master responds with an 8 bit data byte consisting of the register
address. The slave acknowledges and the master sends the repeated start condition [Sr]. Once again, the slave ad-
dress is sent, followed by an eighth bit indicating a read. The slave responds with an acknowledge and the previously
addressed 8 bit data byte; the master then sends a non-acknowledge (NACK). Finally, the master terminates the transfer
with the stop condition [P].
I2C Combined Format - Read
S Slave Address W A Register Address A Sr Slave Address R A
S: Start Condition
W: Write = ‘0’
R: Read = ‘1’
A: Acknowledge (sent by slave)
NACK: Non-Acknowledge (sent by master)
Sr: Repeated Start Condition
P: Stop condition
Slave Address: 7 bit
Register Address: 8 bit
Data: 8 bit
Data
NACK P
Stop Separated Reads
Stop-separated reads can also be used. This format allows a master to set up the register address pointer for a read
and return to that slave at a later time to read the data. In this format the slave address followed by a write command
are sent after a start [S] condition. The SC905 then acknowledges it is being addressed, and the master responds
with the 8-bit register address. The master sends a stop or restart condition and may then address another slave.
After performing other tasks, the master can send a start or restart condition to the SC905 with a read command.
The SC905 acknowledges this request and returns the data from the register location that had previously been set up.
I2C Stop Separated Format - Read
Register Address Setup Access
Master Addresses
other Slaves
S Slave Address W A Register Address A P S Slave Address B
S: Start Condition
W: Write = ‘0’
R: Read = ‘1’
A: Acknowledge (sent by slave)
NACK: Non-Acknowledge (sent by master)
Sr: Repeated Start Condition
P: Stop condition
Slave Address: 7 bit
Register Address: 8 bit
Data: 8 bit
Register Read Access
S/Sr Slave Address A R A Data
NACK P
© 2006 Semtech Corp.
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