SDA5275P データシートの表示（PDF） - Siemens AG

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SDA5275P

ICs for Consumer Electronics MEGATEXT and MEGATEXT PLUS ICs

Siemens AG 

SDA 5273 / 75

SDA 5273-2 / 75-2

Characteristics (cont’d)

TA = 0 to 70 °C

Parameter

Symbol Limit Values Unit Test Condition

min. typ. max.

M3L-Mode Timing (cont’d)

Set-up time SDA to I2CEN- tIM

400

ns

rising edge

Set up time I2CEN to SDA- tIS

400

ns

falling edge

I2CEN-high time

tIH

Delay from SCL-falling edge tDO

until SDA-open drain output

stage changes impedance

1000

400

ns

600 ns

L-SDA level output

impedance

100

Ω

The resulting delay of SDA-output data is the sum of the open drain stage plus the time

determined by the bus capacitance and the external pullup resistor or the impedance of the

internal open drain pulldown transistor respectively.

Wait condition

I2CEN = 0

To force the M3L-master to interrupt the transmission sequence until MEGATEXT is ready for

more data, MEGATEXT can force down SCL after the transmission of a complete byte. At that

time the bus master has to switch its SCL-output to high impedance and check the state of SCL

afterwards.During SCL check I2CEN has to be low.

Delay from SCL-rising edge tDWAIT 500

to SCL forced low for WAIT-

condition

750 ns

An internal pullup transistor restores SCL high level at the end of the WAIT-condition.

SCL-pullup time at the end of tRWAIT 70

WAIT

100 ns

Reference Voltage: VREF

Voltage level

VREF

2.8 3.0 3.5 V

Input leakage current

Il

– 10

10

µA VREF = 3 V

VREF influences the DAC-range, the CVBS-output at pin TCSQ and the CVBS-ADC range.

Semiconductor Group

17

1997-09-01

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