ADV7160KS140 データシートの表示（PDF） - Analog Devices
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ADV7160KS140 Datasheet PDF : 44 Pages
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ADV7160/ADV7162
The SCKOUT signal is essentially the video memory shift con-
trol signal. It is stopped during the screen retrace. Figure 19 shows a
suggested frame buffer to ADV7160/ADV7162 interface. This is a
minimum chip solution and allows the ADV7160/ADV7162 con-
trol the overall graphics system clocking and synchronization.
VIDEO FRAME
BUFFER
LOADOUT
LOADIN
SCKIN ADV7160/
ADV7162
BLANK
SCKOUT
PIXEL
DATA
Figure 19. ADV7160/ADV7162 Interface Using SCKIN
and SCKOUT
PLL
The on-board PLL can be used as an alternative clock source.
This eliminates the need for an external high speed clock gen-
erator such as a crystal oscillator. With the PLL, it is possible to
generate an internal clock whose frequency is a multiple of the PLL
reference frequency (PLLREF). Internal PLL operation is selected
by setting CR56 of Command Register 5 to Logic “1.” The PLL
registers can be programmed to set up the frequency required.
The block diagram of the Phase Locked Loop is shown in Fig-
ure 20. The blocks consist of a phase frequency detector, a
charge pump, a loop filter, a voltage controlled oscillator and a
programmable divider.
PLLREF REFERENCE FPD PHASE
DIVIDER
DETECTOR
FPD
CHARGE
PUMP
FEEDBACK
DIVIDER
VOLTAGE
CONTROLLED
OSCILLATOR
FVCO
O/P
FOUT
DIVIDER
Figure 20. PLL Block Diagram
The phase frequency detector drives the voltage controlled oscil-
lator (VCO), to a frequency that will cause the two inputs to the
phase frequency detector to be matched in frequency and phase.
The corresponding output of the VCO can be calculated as:
VCO = PLLREF Feedback Divider
Reference Divider
The Reference Divider is set by a combination of the contents of
the PLL R Register and the RSEL bit. The PLL R Register has
a resolution of 7 bits. It is programmed by setting the PLL R
Register located at Control Register address 00CH . The PLL
R Register can be set from 01H to 7FH. It should not be set to
00H. If this register contains 00H, then the PLL stops. There-
fore, the Reference Divider can be set from 3 to 129 in steps of
one, or from 130 to 258 in steps of two by setting the RSEL bit.
The RSEL bit is accessed by changing Bit PCR1 of the PLL
Control Register. The Feedback Divider is set by a combina-
tion of the contents of the PLL V Register, the VSEL bit and
the S value. The S value is set up in PCR7 and PCR6 of the
PLL Command Register. This S value allows a better resolu-
tion when setting the Feedback Divider value. The PLL V Reg-
ister has a resolution of 7 bits. It is programmed by setting the
PLL V Register located at Control Register address 00FH .The
PLL V Register can be set from 01H to 7FH. It should not be
set to 00H. If this register contains 00H, then the PLL stops.
Therefore the feedback divider can be set from 12 to 519 in
steps of one, or from 520 to 1038 in steps of two by setting the
VSEL bit. The VSEL bit is accessed by changing bit PCR2 of
the PLL Control Register. The P counter divides the output
from the oscillator by 1, 2, 4 or 8 as determined by PSEL1 and
PSEL0 which are set in bits PCR5 and PCR4 of the PLL Con-
trol Register. This post-scaler is useful in the generation of
lower frequencies as the VCO has been optimized for high
frequency operation.
PLLREF
VCO
(1 + VSEL)(4(V+2) + S)
(1 + RSEL)(R+2)
FVCO
VCO/2
VCO/4
FOUT
VCO/8
FOUT
FVCO
FVCO/2
FVCO/4
FVCO/8
PSEL1 PSEL0
0
0
0
1
1
0
1
1
PSEL1 PSEL0
Figure 21. PLL Transfer Function
The transfer function of the PLL can be summarized by the
block diagram shown in Figure 21.
To optimize the performance of the on-board PLL, the follow-
ing criteria should be followed:
900 kHz
300 kHz
120 MHz
< PLLREF
< FPD
< FVCO
< 40 MHz
< 10 MHz
< 260 MHz
For FVCO > 220 MHz, VSEL should be programmed to logic “0.”
Any lower frequency output can be achieved by using the output
divider.
A jitter performance graph as a function of both FPD and FVCO is
illustrated in Figure 22. It can be seen that jitter decreases with
increasing FVCO and also that jitter decreases with increasing
FPD. For each FOUT, the user should firstly maximize FVCO us-
ing the output divider and then pick PLLREF and reference di-
vide to maximize FPD. When generating multiple output
frequencies from one PLLREF value, an iterative process should
be used to find the PLLREF value that gives the best trade off be-
tween jitter performance and FOUT accuracy.
250
FPD = 0.3MHz
JITTER MEASURED AT 15µs
FPD = 0.42MHz
200
FPD = 0.57MHz
150
FPD = 0.8MHz
FPD = 1.0MHz
FPD = 1.5MHz
FPD = 2.0MHz
100 FPD = 2.7MHz
FPD = 4.0MHz
FPD = 5.3MHz
50
0
50
100
150
200
250
300
VCO FREQUENCY – MHz
Figure 22. PLL Jitter
–18–
REV. 0
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