ADV473KP80 データシートの表示（PDF） - Analog Devices

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ADV473KP80

CMOS 135 MHz True-Color Graphics Triple 8-Bit Video RAM-DAC

Analog Devices 

ADV473

Command Register (CR)

The ADV473 has an internal command register (CR). This reg-

ister is 8 bits wide, CR0–CR7 and is directly mapped to the

MPU data bus on the part, D0–D7. The command register can

be written to or read from. It is not initialized, therefore it must

be set. Figure 4 shows what each bit of the CR register controls

and shows the values it must be programmed to for various

modes of operation.

Color Modes

The ADV473 supports four color modes, 24-bit true-color,

15-bit true-color, 8-bit true-color and 8-bit pseudo-color. The

mode of operation is determined by the S0 and S1 inputs, in

conjunction with CR7 and CR6 of the command register. S0

and S1 are pipelined to maintain synchronization with the video

data. Table III illustrates the modes of operation.

Table III. Color Operation Modes

OL3–OL0 S1, S0 CR7, CR6 Mode

R7–R0

G7–G0

B7–B0

1111

XX

XX

.

.

.

.

.

.

0001

XX

XX

0000

00

00

0000

00

01

0000

00

10

0000

00

11

0000

01

00

0000

01

01

0000

01

10

0000

01

11

0000

10

00

0000

10

01

0000

10

10

0000

10

11

0000

11

00

0000

11

01

0000

11

10

0000

11

11

X = Don’t Care

Overlay Color 15

.

.

Overlay Color 1

24-Bit True-Color

24-Bit True-Color

24-Bit True-Color

Reserved

24-Bit True-Color Bypass

24-Bit True-Color Bypass

24-Bit True-Color Bypass

Reserved

8-Bit Pseudo-Color (Red)

8-Bit Pseudo-Color (Green)

8-Bit Pseudo-Color (Blue)

15-Bit True-Color

8-Bit True-Color Bypass (Red)

8-Bit True-Color Bypass (Green)

8-Bit True-Color Bypass (Blue)

15-Bit True-Color Bypass

XXH

.

.

XXH

R7–R0

R7–R0

R7–R0

Reserved

R7–R0

R7–R0

R7–R0

Reserved

P7–P0

Ignored

Ignored

Orrrrrgg

rrrgggbb

Ignored

Ignored

Orrrrrgg

XXH

.

.

XXH

G7–G0

G7–G0

G7–G0

Reserved

G7–G0

G7–G0

G7–G0

Reserved

Ignored

P7–P0

Ignored

gggbbbbb

Ignored

rrrgggbb

Ignored

gggbbbbb

XXH

.

.

XXH

B7–B0

B7–B0

B7–B0

Reserved

B7–B0

B7–B0

B7–B0

Reserved

Ignored

Ignored

P7–P0

Ignored

Ignored

Ignored

rrrgggbb

Ignored

CR7 CR6

CR5 CR4

CR3 CR2 CR1 CR0

COLOR MODE

SELECT

(SEE TABLE III)

PEDESTAL ENABLE

CONTROL (SETUP)

CR5

0 0 IRE

1 7.5 IRE

CONTROL OUTPUTS

THESE BITS ARE OUTPUT

ONTO THE CR3-CR0 PINS

8-BIT/6-BIT

COLOR SELECT

CR4

0 6-BIT

1 8-BIT

Figure 4. Command Register (CR)

–8–

REV. A

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