UPD16340 データシートの表示（PDF） - NEC => Renesas Technology
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UPD16340 Datasheet PDF : 16 Pages
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µ PD16340
PIN FUNCTIONS
Symbol
Pin Name
Description
/LBLK
Low blanking input
/LBLK = L : All output = L
/HBLK
High blanking input
/HBLK = L : All output = H
/LE
Latch enable input
Latch on a falling edge
HZ
Output high impedance
H: All output set to the high-impedance state
/CLR
A1-A3(6)
B1-B3(6)
Register clear input
RIGHT data input/output Note
LEFT data input/output Note
L: All shift register data cleared to the L level
R,/L = H, the parenthesized pins are used in 6-bit input mode.
A1-A3(6) : Input, B1-B3(6) : Output
R,/L = L, the parenthesized pins are used in 6-bit input mode.
A1-A3(6) : Output, B1-B3(6) : Input
CLK
Clock input
Shift on a rising edge
R,/L
Shift control input
H: Right shift mode
SR1 : A1 → S1.......S94 → B1 (SR2 and SR3 also shift in the same direction.)
Left shift mode
SR1 : B1 → S94.......S1 → A1 (SR2 and SR6 also shift in the same direction.)
IBS
Input mode switch
H: 32-bit shift registers, 3-bit input mode
L: 16-bit shift registers, 6-bit input mode
O1 to O96
High withstand voltage output 80 V, +50/–75 mA MAX.
VDD1
Logic power supply
5 V ± 10 %
VDD2
Driver power supply
10 to 70 V
VSS1
Logic ground
Connect to system ground
VSS2
Driver ground
Connect to system ground
Note In 3-bit input mode, unused I/O pins must be held at the L level.
To use for module, the back side of IC chip must be held at the VSS (GND) level.
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Data Sheet S13685EJ1V0DS00
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