80C196KB データシートの表示（PDF） - Intel

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80C196KB

Advanced 16-bit CHMOS microcomputer ROMless

Intel 

AUTOMOTIVE 8XC196KB

The work-around is to wait for the conversion in

progress to finish before starting the second con-

version Polling or an interrupt will detect the con-

version completion

3 If the unsigned divide instruction (word or byte) is

in the queue as HOLD or READY is asserted the

result may be incorrect TechBit (MC1791)

(B-step only )

DIFFERENCES BETWEEN THE

80C196KA AND THE 80C196KB

The 8XC196KB is identical to 8XC196KA except for

the following differences

1 ALE is high after reset on the 80C196KB instead

of low as on the 80C196KA

2 The DJNZW instruction is not guaranteed to work

on the 80C196KB (A-step only )

3 The HOLD HLDA bus protocol is available on the

80C196KB

CONVERTING FROM OTHER 8096BH

FAMILY PRODUCTS TO THE

80C196KB

The following list of suggestions for designing an

809XBH system will yield a design that is easily con-

verted to the 80C196KB

1 Do not base critical timing loops on instruction or

peripheral execution times

2 Use equate statements to set all timing parame-

ters including the baud rate

3 Do not base hardware timings on CLKOUT or

XTAL1 The timings of the 80C196KB are differ-

ent than those of the 8X9XBH but they will func-

tion with standard ROM EPROM Peripheral type

memory systems

4 Make sure all inputs are tied high or low and not

left floating

5 Indexed and indirect operations relative to the

stack pointer (SP) work differently on the

80C196KB than on the 8096BH On the 8096BH

the address is calculated based on the un-updat-

ed version of the stack pointer The 80C196KB

uses the updated version The offset for POP SP

and POP nn SP instructions may need to be

changed by a count of 2

6 The VPD pin on the 8096BH has changed to a

VSS pin on the 80C196KB

OTHER DESIGN CONSIDERATIONS

(KB B-0 to KB C-1)

1 The NMI pin on the KB ROM (C-1) has a weak

pulldown IIH1 max is 100 mA The KB ROM (B-0)

did not have a pulldown on NMI If KB ROM (B-0)

designs have NMI tied to VCC the NMI pin must

be tied to VSS If NMI is tied to VSS or is floating

it is okay

2 The ALE RD and INST pins on the KB ROM

(C-1) have stronger pullups during RESET than

on the KB ROM (B-0) IIL1 is b7 mA on the KB

ROM (C-1) compared to b1 2 mA on the KB

ROM (B-0) Designs which pull these pins low to

enter ONCE mode must have strong enough pull-

downs to overcome the pullups

3 Pin on the PLCC package on the KB ROM (B-0)

was the CDE pin That function did not work so

the pin was assigned to VSS On the KB ROM

(C-1) this pin is tied directly to VSS on the device

and MUST be tied to VSS externally

4 Several AC DC specifications have changed

(See Data Sheet Revision History review them

carefully )

16

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