SP791 データシートの表示（PDF） - Signal Processing Technologies
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SP791 Datasheet PDF : 19 Pages
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Vcc
RESET
THRESHOLD
CE IN
CE OUT
RESET
15µs
100µs
100µs
Figure 7. Reset and Chip-Enable Timing
The 10ns maximum CE propagation from CE
IN to CE OUT enables the SP791 to be used with
most µPs.
CHIP-ENABLE INPUT
CE IN is high impedance (disabled mode) while
RESET is asserted.
During a power-down sequence where VCC falls
below 4.65V, CE IN assumes a high impedance
state when the voltage at CE IN goes high or
15µs after RESET is asserted, whichever
occurs first, (Figure 7).
During a power-up sequence, CE IN remains
high impedance until RESET is deasserted.
In the high-impedance mode, the leakage
currents into this input are less than 1µA over
temperature. In the low-impedance mode, the
impedance of CE IN appears as a 65Ω resistor
in series with the load at CE OUT.
The propagation delay through the CE
transmission gate depends on both the source
impedance of the drive to CE IN and the
capacitive loading on CE OUT (see the Chip-
Enable Propagation Delay vs. CE OUT Load
Capacitance graph in the Typical Operating
Characteristics). The CE propagation delay is
defined from the 50% point on CE IN to the 50%
point on CE OUT using a 50Ω driver with 50pF
load capacitance as in Figure 8. For minimum
propagation delay, minimize the capacitive load
at CE OUT and use a low output-impedance
driver.
CHIP-ENABLE OUTPUT
In the enabled mode, the impedance of CE OUT
is equivalent to 65Ω in series with the source
driving CE IN. In the disabled mode, the 65Ω
transmission gate is off and CE OUT is actively
pulled to VOUT. This source turns off when the
transmission gate is enabled.
50Ω Driver
+5V
Vcc
Corporation
CE IN CE OUT
GND
50pF
CLOAD
SP791DS/08
Figure 8. CE Propagation Delay Test Circuit
SP791 Low Power Microprocessor Supervisory with Battery Switch-Over
11
© Copyright 2000 Sipex Corporation
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