4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory
SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A
Data Sheet
ADDRESS A18-0
BES#1
BEF#
OE#1
TOEH
TBE
TOE
TOES
WE#
DQ6
TWO READ CYCLES
WITH SAME OUTPUTS
349 ILL F07.6
Note 1. For SST31LF041A/043A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#.
FIGURE 9: FLASH TOGGLE BIT TIMING DIAGRAM
SIX-BYTE CODE FOR SECTOR-ERASE
TSE
ADDRESS A18-0
5555 2AAA
5555
5555
2AAA
SAX
BES#1
BEF#
OE#1
WE#
TWP
DQ7-0
AA
55
80
AA
55
30
SW0
SW1
SW2
SW3
SW4
SW5
349 ILL F08.8
Note: The device also supports BEF# controlled Sector-Erase operation. The WE# and BEF# signals are
interchangeable as long as minimum timings are met. (See Table 12)
SAX = Sector Address
Note 1. For SST31LF041A/043A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#.
FIGURE 10: WE# CONTROLLED FLASH SECTOR-ERASE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
15
S71107-03-000 5/01 349