SST34HF1681 データシートの表示（PDF） - Silicon Storage Technology
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SST34HF1681 Datasheet PDF : 30 Pages
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16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory
SST34HF1681
Advance Specifications
SIX-BYTE CODE FOR BLOCK-ERASE
TBE
ADDRESS A19-0
5555 2AAA
5555
5555
2AAA
BAX
BEF#
OE#
WE#
RY/BY#
DQ15-0
TWP
TBY
XXAA XX55
XX80
XXAA
XX55
XX50
Note: This device also supports BEF# controlled Block-Erase operation. The WE# and BEF#
signals are interchageable as long as minimum timings are met. (See Table 15)
BAX = Block Address
X can be VIL or VIH, but no other value.
FIGURE 12: FLASH WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM
TBR
VALID
561 ILL F13.2
SIX-BYTE CODE FOR SECTOR-ERASE
TSE
ADDRESS A19-0
5555 2AAA
5555
5555
2AAA
SAX
BEF#
OE#
WE#
RY/BY#
DQ15-0
TWP
TBY
XXAA XX55
XX80
XXAA
XX55
XX30
Note: This device also supports BEF# controlled Sector-Erase operation. The WE# and BEF#
signals are interchageable as long as minimum timings are met. (See Table 15)
SAX = Sector Address
X can be VIL or VIH, but no other value.
FIGURE 13: FLASH WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
TBR
VALID
561 ILL F14.2
©2001 Silicon Storage Technology, Inc.
21
S71214-00-000 12/01 561
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