Preliminary Specifications
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
ADDRESS AMS-0
CE#
TAS
OE#
5555
TAH
TCP
2AAA
TCPH
5555
ADDR
TDS
INTERNAL PROGRAM OPERATION STARTS
TBP
TDH
WE#
TCH
DQ15-0
XXAA
TCS
XX55
XXA0
DATA
SW0 SW1
SW2
WORD
(ADDR/DATA)
1223 F05.3
FIGURE
Note:
AMS = Most significant address
AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value
5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS AMS-0
CE#
OE#
WE#
TOEH
TCE
TOE
TOES
DQ7
DATA
DATA#
DATA#
DATA
Note: AMS = Most significant address
AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402
1223 F06.2
FIGURE 6: DATA# POLLING TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
16
S71223-03-000
11/03