SST39VF1601-90-4I-B3K データシートの表示（PDF） - Silicon Storage Technology

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SST39VF1601-90-4I-B3K

16 Mbit / 32 Mbit / 64 Mbit (x16) Multi-Purpose Flash Plus

Silicon Storage Technology 

16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 / SST39VF6401

SST39VF1602 / SST39VF3202 / SST39VF6402

Preliminary Specifications

ADDRESS AMS-0

CE#

OE#

TOEH

TCE

TOE

TOES

WE#

DQ6 and DQ2

Note:

TWO READ CYCLES

WITH SAME OUTPUTS

AMS = Most significant address

AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402

1223 F07.3

FIGURE 7: TOGGLE BITS TIMING DIAGRAM

ADDRESS AMS-0

SIX-BYTE CODE FOR CHIP-ERASE

5555 2AAA

5555

5555

2AAA

5555

TSCE

CE#

OE#

WE#

TWP

DQ15-0

XXAA

SW0

XX55

SW1

XX80

SW2

XXAA

SW3

XX55

SW4

XX10

SW5

Note:

This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 17)

AMS = Most significant address

AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402

WP# must be held in proper logic state (VIH) 1 µs prior to and 1 µs after the command sequence

X can be VIL or VIH, but no other value

FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM

1223 F08.4

©2003 Silicon Storage Technology, Inc.

17

S71223-03-000

11/03

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