SST49LF004B-33-4C-WHE データシートの表示（PDF） - Silicon Storage Technology
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SST49LF004B-33-4C-WHE Datasheet PDF : 36 Pages
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4 Mbit Firmware Hub
SST49LF004B
Firmware Memory Write Cycle
EOL Data Sheet
TABLE 5: FIRMWARE MEMORY WRITE CYCLE
Clock
Cycle
1
Field
Name
START
Field Contents
LAD[3:0]1
1110
LAD[3:0]
Direction
IN
2
IDSEL
0000 to 1111
IN
3-9
MADDR
YYYY
IN
10
MSIZE
0000 (1 Byte)
IN
11
DATA
ZZZZ
IN
12
DATA
ZZZZ
IN
13
TAR0
1111
IN then Float
14
TAR1
1111 (float)
Float then OUT
15
RSYNC
0000
OUT
16
TAR0
1111
OUT then Float
17
TAR1
1111 (float)
Float then IN
1. Field contents are valid on the rising edge of the present clock cycle.
Comments
LFRAME# must be active (low) for the device to
respond. Only the last field latched before LFRAME#
transitions high will be recognized. The START field
contents (1110b) indicate a Firmware Memory Write
cycle.
Indicates which SST49LF004B device should
respond. If the IDSEL (ID select) field matches the
value of ID[3:0], the device will respond to the mem-
ory cycle.
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
The MSIZE field indicates how many bytes will be
transferred during multi-byte operations. The device
only supports single-byte writes. MSIZE=0000b
ZZZZ is the least-significant nibble of the data byte.
ZZZZ is the most-significant nibble of the data byte.
In this clock cycle, the host drives the bus to all '1's and
then floats the bus prior to the next clock cycle. This is
the first part of the bus “turnaround cycle.”
The SST49LF004B takes control of the bus during this
cycle.
During this clock cycle, the device generates a “ready
sync” (RSYNC) indicating that the device has received
the input data.
In this clock cycle, the SST49LF004B drives the bus to
all '1's and then floats the bus prior to the next clock
cycle. This is the first part of the bus “turnaround cycle.”
The host resumes control of the bus during this cycle.
T5.0 1307
LCLK
LFRAME#
LAD[3:0]
Start IDSEL
MADDR
MSIZE
DATA
TAR0 TAR1 RSYNC
1110b 0000b A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] 0000b D[3:0] D[7:4] 1111b Tri-State 0000b TAR
1307 F04.0
FIGURE 5: FIRMWARE MEMORY WRITE CYCLE WAVEFORM
©2007 Silicon Storage Technology, Inc.
13
S71307-03-EOL
12/07
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