ST7232A データシートの表示（PDF） - STMicroelectronics

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ST7232A

8-BIT MICROCONTROLLER WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFACE

STMicroelectronics 

ST7232A

RESET SEQUENCE MANAGER (Cont’d)

The RESET pin is an asynchronous signal which

plays a major role in EMS performance. In a noisy

environment, it is recommended to follow the

guidelines mentioned in the electrical characteris-

tics section.

6.3.3 External Power-On RESET

To start up the microcontroller correctly, the user

must ensure by means of an external reset circuit

that the reset signal is held low until VDD is over

the minimum level specified for the selected fOSC

frequency.

Figure 14. RESET Sequences

A proper reset signal for a slow rising VDD supply

can generally be provided by an external RC net-

work connected to the RESET pin.

6.3.4 Internal Watchdog RESET

The RESET sequence generated by a internal

Watchdog counter overflow is shown in Figure 14.

Starting from the Watchdog counter underflow, the

device RESET pin acts as an output that is pulled

low during at least tw(RSTL)out.

RUN

EXTERNAL

RESET

ACTIVE

PHASE

RUN

WATCHDOG

RESET

ACTIVE

PHASE

RUN

EXTERNAL

RESET

SOURCE

RESET PIN

WATCHDOG

RESET

th(RSTL)in

tw(RSTL)out

WATCHDOG UNDERFLOW

INTERNAL RESET (256 or 4096 TCPU)

VECTOR FETCH

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