STA003T データシートの表示（PDF） - STMicroelectronics

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STA003T

MPEG 2.5 LAYER III AUDIO DECODER

STMicroelectronics 

STA003T

Figure 6. PLL and Clocks Generation System

PLLCTL_N reg

XTI

N

PFD

PLLCTL_M reg

M

PLLFRAC reg

PLLFRAC

Switching

Circuit

This signal is used as interrupt signal inside

STA003T.

Within a WorldSpace Broadcast Frame, there are

a fixed number of PCM samples, depending on

the nominal audio sampling rate (Fig. 7).

Using this information, with the SRC_INT signal

Figure 7. WorldSpace BC Framing

CP

R

C

C

VCO

Disable PLL

MFSDF(X) reg

X

OCLK

XTI2OCLK

S

DCLK

XTI2DSPCLK

as external timer source, STA003T performs the

compensation of the audio sampling rate.

The sampling rate control is done by the

STA003T core, by setting PLLFRAC internal reg-

ister. The PLLFRAC value is updated, in steps of

few ppms, by Update PLLFRAC signal.

tLOW

tINT

SRC_INT

BC Frame Time Lenght:

MPEG Frames into 1 BC Frame:

PCM Samples into 1 BC Frame:

432 ms

18 for 48 & 24 KHz

12 for 32 & 16 KHz

9 for 12 KHz

6 for 8 KHz

20736 for 48 KHz

10368 for 24 KHz

13824 for 32 KHz

6912 for 16 KHz

5184 for 12 KHz

3456 for 8 KHz

7/32

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