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STK621-041A-E データシートの表示(PDF) - SANYO -> Panasonic

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STK621-041A-E Datasheet PDF : 13 Pages
First Prev 11 12 13
STK621-041,621-041A-E
STK621-041, 041A-E Logical Timing Chart
HIN1, 2, 3
OFF
ON
LIN1, 2, 3
VDD
(4)
Under voltage protection reset voltage
(2)
VB1, 2, 3
(3)
ON
(1)
UVW (upper)
OFF
(1)
UVW (lower)
* "-" Line current
(+- forward)
FAULT
About 10µs
About 10µs
ITF02447
* The ‘‘-’’ line current shows only the short circuit current in order to explain overcurrent protection operation.
Notes
1. (1) is the timing chart when the anti-simultaneous ON circuit in the signal input block has operated.
(Note that a dead time must be externally set to prevent a short circuit due to switching delay.)
2. When the lower phase VDD is insufficient, all gate output signals is set to OFF and the FAULT output is set Low.
However, unlike the upper phase protection operation, the latch state is canceled and the FAULT output is set High
approximately 10µs after the voltage recovers to normal and all six phase inputs go OFF. (2)
3. When the upper phases VB1, VB2 and VB3 are insufficient (3), only the upper phase outputs of the corresponding
phases are set to OFF, and FAULT output is not performed. However, the output OFF latch status continues while
the input signals are ON. After VB1, VB2 and VB3 recover, the outputs are returned to operating status by re-
inputting the signals to the upper phases.
4. Overcurrent protection operation is as follows. (This describes the case when a load short circuit occurs only during
the gray portion (4).) When an overcurrent flows, the HIC internal overcurrent protection circuit operates and
performs control to set the IGBT for all phases to OFF. In addition, the FAULT output is also set Low at this time.
After protection operation ends, the latch status is canceled and the FAULT output is set High approximately 10µs
after all six inputs go OFF.
No. A0483-12/13

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