STM32F050C4 データシートの表示（PDF） - STMicroelectronics

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STM32F050C4

Low- and medium-density advanced ARM™-based 32-bit MCU with up to 32 Kbytes Flash, timers, ADC and comm. interfaces

STMicroelectronics 

Functional overview

STM32F050xx

3.7

General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions.

The I/O configuration can be locked if needed following a specific sequence in order to avoid

spurious writing to the I/Os registers.

3.8

Direct memory access controller (DMA)

The 5-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory

and memory-to-peripheral transfers.

The DMA supports circular buffer management, removing the need for user code

intervention when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software

trigger on each channel. Configuration is made by software and transfer sizes between

source and destination are independent.

DMA can be used with the main peripherals: SPI, I2S, I2C, USART, all TIMx timers (except

TIM14) and ADC.

3.9

3.9.1

3.9.2

Interrupts and events

Nested vectored interrupt controller (NVIC)

The STM32F050xx family embeds a nested vectored interrupt controller able to handle up

to 32 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M0) and 4

priority levels.

● Closely coupled NVIC gives low latency interrupt processing

● Interrupt entry vector table address passed directly to the core

● Closely coupled NVIC core interface

● Allows early processing of interrupts

● Processing of late arriving higher priority interrupts

● Support for tail-chaining

● Processor state automatically saved

● Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

Extended interrupt/event controller (EXTI)

The external interrupt/event controller consists of 24 edge detector lines used to generate

interrupt/event requests and wake-up the system. Each line can be independently

configured to select the trigger event (rising edge, falling edge, both) and can be masked

independently. A pending register maintains the status of the interrupt requests. The EXTI

can detect an external line with a pulse width shorter than the internal clock period. Up to 39

GPIOs can be connected to the 16 external interrupt lines.

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Doc ID 023683 Rev 1

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