ML53612 データシートの表示（PDF） - Oki Electric Industry

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ML53612

64-Channel Full Duplex H.100/H.110 CT Bus System Interface and Time-Slot Interchange

Oki Electric Industry 

––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– s ML53612 s

APLL CLKREF Frequency [3:0] (C_ [7:4]) (Read/Write)

Put APLL in Power-down (C_[2] = 1) when changing APLL CLKREF Frequency.

0h

→ 65.536 MHz (32 X 2.048 MHz) (Default)

1h

→ 49.152 MHz (24 X 2.048 MHz)

2h

→ 32.768 MHz (16 X 2.048 MHz)

3h

→ 16.384 MHz (8 X 2.048 MHz)

4h

→ 8.192 MHz (4 X 2.048 MHz)

5h

→ 4.096 MHz (2 X 2.048 MHz)

6h

→ 2.048 MHz

7h

→ Reserved

8h

→ 49.408 MHz (32 X 1.544 MHz)

9h

→ 37.056 MHz (24 X 1.544 MHz)

Ah

→ 24.704 MHz (16 X 1.544 MHz)

Bh

→ 12.352 MHz (8 X 1.544 MHz)

Ch

→ 6.176 MHz (4 X 1.544 MHz)

Dh

→ 3.088 MHz (2 X 1.544 MHz)

Eh

→ 1.544 MHz

Fh

→ 1.536 MHz

Oki Semiconductor

17

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