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IR3Y38 データシートの表示(PDF) - Sharp Electronics

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IR3Y38 Datasheet PDF : 21 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
IR3Y38M
PRECAUTIONS
Each VCC1 to VCC6 pin corresponds to the each
GND1 to GND6 pin. Connect a ceramic capacitor
as near the IC as possible between each
corresponding VCC pin and GND pin.
The GND1 pin is the ground of the CDS/ADC
circuit handling a weak signal. Pay careful attention
to the board layout of the GND1 pattern in order to
avoid the potential fluctuation of the GND1 caused
by the current of the other GND pins. Especially
pay attention to the current of the GND6 pin's
flowing spiky current.
converter is controllable by the voltage of the
VLOGIC pin, but take care that the high level voltage
does not fall below about 1.5 V, in spite of making
the VLOGIC pin 0 V. This may cause the latch up of
the following logic ICs if the power supply of this IC
rises up faster than the power supply of the
following logic. To avoid this problem, it is
recommended to make the ‰ pin low until the
voltage of the logic power supply becomes stable.
Take care too that the high level voltage does not
rise above about VCC – 1.0 V, in spite of making
the VLOGIC pin the VCC potential.
All the GND pins must be at the same potential
and not open. And keep the potential difference of
each VCC pin within 0.3 V.
The high level voltage of the outputs of the A/D
Restore the value of the serial register when setting
up the power supply or making the ‰ pin high
because the value will have been removed in that
case.
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
Supply voltage
VCC1-VCC6
Input voltage
VIN
Power consumption
PD
PD derating ratio
Operating temperature
TOPR
Storage temperature
TSTG
(Unless otherwise specified, TA = +25 ˚C)
CONDITIONS
RATING
UNIT
7
V
–0.3 to VCC + 0.3
V
TA ≤ +25 ˚C
570
mW
TA > +25 ˚C
4.5
mW/˚C
–30 to +70
˚C
–55 to +150
˚C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL APPLICABLE PINS
Supply voltage
VCC1-VCC6
Standard CCD input signal level VCCD
CCDIN
Input "Low" voltage
Input "High" voltage
VIL ‡, SCK, SDATA,
‰, Â, fl/H1, fl/H2,
VIH fl/H3, Î, Ô, Å
S/H pulse width
tWS/H Â, fl/H1, fl/H2, fl/H3
Clamp pulse width
tWC
Î, Å
A/D converter clock frequency
fADCK
ADCK
Serial interface clock frequency fSCK
SCK
RATING
4.75 to 5.25
200
0 to 0.7
2.1 to VCC
≥ 12
≥ 1.5
≤ 18
≤ 300
UNIT
V
mVp-p
V
V
ns
µs
MHz
kHz
12

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