83C196NP データシートの表示（PDF） - Intel

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83C196NP

COMMERCIAL CHMOS 16-BIT MICROCONTROLLER

Intel 

8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER

Name

EPA3:0

EPORT.3:0

EXTINT0

EXTINT1

EXTINT2

EXTINT3

HLDA#

HOLD#

INST

NMI

Table 8. Pin Descriptions (Continued)

Type

Description

Multiplexed

with

I/O Event Processor Array (EPA) Input/Output pins

P1.3:0

These are the high-speed input/output pins for the EPA

capture/compare channels. For high-speed PWM applications, the

outputs of two EPA channels (either EPA0 and EPA1 or EPA2 and

EPA3) can be remapped to produce a PWM waveform on a shared

output pin.

I/O Extended Addressing Port

A19:16

This is a 4-bit, bidirectional, memory-mapped I/O port. The pins are

shared with the extended address bus A19:16.

I External Interrupts

P2.2

In normal operating mode, a rising edge on EXTINTx sets the

P2.4

EXTINTx interrupt pending bit. EXTINTx is sampled during phase 2 P3.6

(CLKOUT high). The minimum high time is one state time.

P3.7

In powerdown mode, asserting the EXTINTx signal for at least 1

state time causes the device to resume normal operation. The

interrupt need not be enabled, but the pin must be configured as a

special-function input. If the EXTINTx interrupt is enabled, the CPU

executes the interrupt service routine. Otherwise, the CPU executes

the instruction that immediately follows the command that invoked

the power-saving mode.

In idle mode, asserting any enabled interrupt causes the device to

resume normal operation.

O Bus Hold Acknowledge

P2.6

This active-low output indicates that the CPU has released the bus

as the result of an external device asserting HOLD#.

I Bus Hold Request

P2.5

An external device uses this active-low input signal to request

control of the bus. This pin functions as HOLD# only if the pin is

configured for its special function and the bus-hold protocol is

enabled. Setting bit 7 of the window selection register enables the

bus-hold protocol.

O Instruction Fetch

—

This active-high output signal is valid only during external memory

bus cycles. When high, INST indicates that an instruction is being

fetched from external memory. The signal remains high during the

entire bus cycle of an external instruction fetch. INST is low for data

accesses, including interrupt vector fetches and chip configuration

byte reads. INST is low during internal memory fetches.

I Nonmaskable Interrupt

—

In normal operating mode, a rising edge on NMI generates a

nonmaskable interrupt. NMI has the highest priority of all prioritized

interrupts. Assert NMI for greater than one state time to guarantee

that it is recognized.

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