TDA1315H/N2 データシートの表示（PDF） - Philips Electronics

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TDA1315H/N2

Digital audio input/output circuit(DAIO)

Philips Electronics 

Philips Semiconductors

Digital audio input/output circuit (DAIO)

Product specification

TDA1315H

Fig.8 Multi-byte transfer.

DAIO control

Under microcontroller control, there is also a transmit

mode available. Therefore, setting the device

configuration is slightly different from the stand-alone

mode. Most functions or modes can be set by pins or by

the control register or by both. Negative logic is used to

implement this ‘OR’ function. The initial setting of the

control register is all ones. For most functions, the

TDA1315H can be configured only by pins, as explained

for the stand-alone mode. The principle of this type of

control is illustrated in Fig.9. However, for changing

CLKSEL, I2SSEL and the receive/transmit mode, there is

a configuration register, which is updated only by an

externally supplied STROBE signal. This allows

synchronization with other ICs.

At pin LDATA, control information is first entered serially

into a shift register and then latched in the control register

when complete. The bits of the second byte (6 are used)

of this register are internally ORed with their

corresponding pins, so that either a LOW or a logic 0 bit

will result in a logic 0 state (active LOW). These combined

states are then entered in the status register. The resulting

CLKSEL and I2SSEL information is supplied to the

configuration register, i.e. these bits will only be executed

in the TDA1315H, together with the receive/transmit bit,

after a STROBE has been received. This applies to the

host mode. In the stand-alone mode, the configuration

register is transparent and any configuration changes are

executed immediately. When the TDA1315H status is

read, the contents of the status register are output serially

at pin LDATA, thereby reflecting the ‘OR’ combination of

configuration control bits and associated pins (negative

logic). The microcontroller is thereby able to determine

whether a pin is open-circuit or tied to ground.

When a STROBE is applied in the receive mode (to switch

to transmit mode), the outputs WS and SCK are disabled

one or two system clock periods after the rising edge of

STROBE. At the same time SYSCLKO will be forced LOW

and will be disabled one system clock later.

In the transmit mode it is possible to set the

receive/transmit bit to zero and then poll the locking status

of the TDA1315H and wait with a STROBE until the

TDA1315H is in-lock. This method can be used to check

whether there is an IEC source, since the TDA1315H will

not lock without one. It should be noted that the locking

status bit and the UNLOCK pin are only valid, i.e. its value

has a meaning, when you are in either the receive mode or

the receive/transmit bit is set to zero in the transmit mode.

When the configuration is changed to the receive mode,

WS, SCK, INVALID and SYSCLKO outputs are enabled

one or two system clock periods after the falling edge of

STROBE. SYSCLKO will always be initially LOW, for a

short time, and then pulses will appear always starting with

the rising edge.

In general WS and SCK outputs are always

enabled/disabled simultaneously. Output INVALID will

only be enabled when SD, WS and SCK are all enabled.

The mode timing is illustrated in Fig.10.

The control register consists of two bytes. The meaning of

the control register bits is given in Tables 8 and 9. All bits

default to a logic HIGH state after a reset to the

TDA1315H. This requires a reset for proper initialization

when CTRLMODE is changed after power-up. The LSB

(bit 0) is always transferred first.

1995 Jul 17

17

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