TDA7462 データシートの表示（PDF） - STMicroelectronics

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TDA7462

DUAL AUDIOPROCESSOR WITH COMPANDER AND SUBWOOFER OUTPUT

STMicroelectronics 

TDA7462

I2C BUS INTERFACE DESCRIPTION

Interface Protocol

The interface protocol comprises:

- a start condition (S)

- a chip address byte (the LSB bit determines

read / write transmission)

- a subaddress byte

- a sequence of data (N-bytes + acknowledge)

- a stop condition (P)

- the max. Clock Speed is 500kbits/s

CHIP ADDRESS

8 Bit

MSB

LSB

MSB

S 1 0 0 0 1 0 0 R/W ACK I3 I2

SUBADDRESS

8 Bit

DATA 1 ... DATA n

8 Bit

LSB

MSB

LSB

I1 I0 A3 A2 A1 A0 ACK

DATA

ACK P

S = Start

R/W = "0" -> Receive Mode (Chip could be

programmed by µP)

"1" -> Transmission Mode (Data could be

received by µP)

ACK = Acknowledge

P = Stop

TRANSMITTED DATA (send mode)

MSB

X X X X ST SM

SM = Soft mute activated

ST = Stereo

X = Not Used

LSB

XX

The transmitted data is automatic updated after

each ACK. Transmission can be repeated without

new chipaddress.

Reset Condition

A Power On reset (POR) is invoked if the supply

voltage is below than 3.5V. After that the follow-

ing data is written automatically into the registers

of all subaddresses:

MSB

LSB

1

1

1

1

1

1

1

0

The programming after POR is marked bold-face

/ underlined in the programming tables.

With this programming all the outputs are muted

to VREF (VOUT = VDD/2).

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