TDA8769 データシートの表示（PDF） - Philips Electronics

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TDA8769

12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling

Philips Electronics 

Philips Semiconductors

12-bit, 60/80/105 Msps Analog-to-Digital Converter

(ADC) Nyquist/high IF sampling

Objective specification

TDA8769

SYMBOL PARAMETER

CONDITIONS

TEST(1)

MIN.

TYP.

MAX. UNIT

Reference voltage input: pin VREF; note 3

Vref(FS) full-scale fixed fi = 25 MHz;

−

voltage

fCLK = 105 Msps

Vi(p-p)

input voltage

Vi = VIN − VINN;

−

(peak-to-peak VVREF = VCCA3 − 1.75 V;

value)

Vi(CM) = VCCA3 − 1.6 V

Iref

input current

−

Full-scale voltage controlled regulator output: pin FSREF

Vo(FS)

1.9 V full-scale

−

output voltage

IL(FS)

load current

−

Digital outputs: pins D11 to D0 and IR

VCCA3 − 1.75 −

V

1.9

−

V

0.3

10

µA

VCCA3 − 1.75 −

V

1

2

mA

OUTPUT LEVELS

VOL

LOW-level

IOL = 2 mA

output voltage

VOH

HIGH-level

IOH = −0.4 mA

output voltage

IOZ

output current in output level between

3-state

0.5 V and VCCO

TIMING; see Fig. 3

td(s)

sampling delay CL = 10 pF; note 4

th(o)

output hold time CL = 10 pF

td(o)

output delay

CL = 10 pF

3-STATE OUTPUT DELAY

tdZH

enable to HIGH

state

tdZL

enable to LOW

state

tdHZ

disable from

HIGH state

tdLZ

disable from

LOW state

DGND

−

VCCO − 0.5 −

−20

−

−

(tbf)

(tbf)

3.7

−

4.6

−

2.8

−

7.5

−

7.2

−

2.9

DGND + 0.5 V

VCCO

V

+20

µA

(tbf)

ns

−

ns

(tbf)

ns

−

ns

−

ns

−

ns

−

ns

Timing complete conversion signal: pin CCS

td(CCS)

complete

conversion

signal delay

CL = 10 pF; see Table 4

and Fig 4

DEL0 = LOW;

DEL1 = HIGH

DEL0 = HIGH;

DEL1 = LOW

DEL0 = HIGH;

DEL1 = HIGH

−

0

−

ns

−

1.2

−

ns

−

2.2

−

ns

2003 Dec 09

9

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