TDA9106A データシートの表示（PDF） - STMicroelectronics
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TDA9106A Datasheet PDF : 30 Pages
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TDA9106A
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VDD
VIN
VESD
Tstg
Tj
Toper
Parameter
Supply Voltage (Pin 18)
Supply Voltage (Pin 39)
Max Voltage on Pin 6
Pins 15, 21, 22, 23
Pin 1
Pin 4
Pins 3, 33,34,37,38,40,41
Pin 16
Pins 8, 9, 10, 11, 12, 13, 14, 25, 27, 30
ESD susceptibility
Human Body Model,100pF Discharge through 1.5kΩ
EIAJ Norm,200pF Discharge through 0Ω
Storage Temperature
Junction Temperature
Operating Temperature
Value
13.5
5.7
1.8
12
3.6
4
5
6
8
2
300
-40, +150
+150
0, +70
Unit
V
V
V
V
V
V
V
V
V
kV
V
oC
oC
oC
THERMAL DATA
Symbol
Parameter
Rth (j-a) Junction-ambient Thermal Resistance
Max.
Value
65
Unit
oC/W
SYNCHRO PROCESSOR
Operating Conditions
Symbol
HsVR
MinD
Mduty
VsVR
VSW
VSmD
VextM
Parameter
Horizontal Sync Input Voltage
Minimum Horizontal Input Pulses Duration
Maximum Horizontal Input Signal Duty Cycle
Vertical Sync Input Voltage
Minimum Vertical Sync Pulse Width
Maximum Vertical Sync Input Duty Cycle
Maximum Vertical Sync Width on TTL
H/Vcomposite or S/G
Test Conditions
Pin 38
Pin 38
Pin 38
Pin 33
Pin 33
Pin 33
Pins 1, 38
Electrical Characteristics (VDD = 5V, Tamb = 25oC)
Symbol
Parameter
VSGDC S/G Clamped DC Level
ISGbias Internal Diode Bias Current
VSGTh Slicing Level (see application design choice)
VINTH H o r iz on t al a n d V ert i cal I npu t V o lta ge
(Pins 33,38)
RIN Horizontal and Vertical Pull-Up Resistor
VOut Output Voltage (Pins 35,36,37)
TfrOut Falling and Rising Output CMOS Buffer
VHlock Horizontal 1st PLL Lock Output Status (Pin 37)
VoutT Extracted Vsync Integration Time (% of TH) on
H/V Composite or S/G
Test Conditions
Pin 1, I1 = -1µA
Pin 1, V1 = 1.6V
Pin 1
Low Level
High Level
Pins 33,38
Low level
High Level
Pins 35,36,37
Cout = 20pF
Locked
Unlocked
Pin 35, C0 = 820pF
Min.
0
0.7
0
5
Min.
2.2
26
Typ.
Typ.
1
10
0.2
200
0
5
100
0
5
35
Max.
5
25
5
15
750
Unit
V
µs
%
V
µs
%
µs
Max.
0.8
Unit
V
µA
V
V
V
kΩ
V
V
ns
V
V
%
5/30
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