TEA1202TS_02 データシートの表示（PDF） - Philips Electronics

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TEA1202TS_02

0.95 V starting power unit

Philips Electronics 

Philips Semiconductors

0.95 V starting power unit

Preliminary specification

TEA1202TS

SYMBOL

PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

General characteristics

Vref

reference voltage

Iq

quiescent current at

pin UPOUT/DNIN

all blocks operating

1.165 1.190 1.215 V

−

270

−

µA

Tamb

Tmax

ambient temperature

internal temperature for cut-off

−20

+25

+80

°C

150

160

170

°C

Notes

1. The undervoltage lockout level shows wide specification limits since it decreases at increasing temperature. When

the temperature increases, the minimum supply voltage of the digital control part of the IC decreases and therefore

the correct operation of this function is guaranteed over the whole temperature range. The undervoltage lockout level

is measured at pin UPOUT/DNIN.

2. When VI(dwn) is lower than the target output voltage but higher than 2.2 V, the P-type power MOSFET will remain

conducting (duty factor is 100%), resulting in VO(dwn) following VI(dwn).

3. The quiescent current is specified as the current in to pin UPOUT/DNIN (pin 4) in the upconversion configuration at

VI = 1.20 V and VO = 3.30 V, using L1 = 6.8 µH, R1 = 150 kΩ and R2 = 91 kΩ.

4. The current limit is defined by resistor R10. This resistor must have 1% accuracy.

5. The specified efficiency is valid when using an output capacitor having an ESR of 0.1 Ω and an inductor of 6.8 µH

with an ESR of 0.05 Ω and a sufficient saturation current level.

6. The specified start-up time is the time between the connection of a 1.20 V input voltage source and the moment the

output reaches 3.30 V. The output capacitance equals 100 µF, the inductance equals 6.8 µH and no load is present.

7. V4 is the voltage at pin UPOUT/DNIN. If the applied HIGH-level voltage is less than V4 − 1 V, the quiescent current

of the device will increase.

8. Take care regarding total dissipation if output current ILDO > 50 mA and drop voltage Vdrop > 2 V.

9. The drop-out voltage is defined as the voltage between the input and the output of the LDO when the output voltage

has dropped 100 mV below its nominal value. The drop-out voltage is measured while the LDO input voltage is

decreasing.

10. The output voltage of each LDO is defined by external feedback resistors. These resistors must have 1% accuracy.

11. ∆Vline = V-----L-∆-D---V-O---L--×-D---O∆----V----I × 100 %/V.

12. ∆Vload = V-----L--D--∆--O--V---×-L---D∆---O-I--L--D----O-- × 100 %/mA.

13. Measured with a sine wave at fi = 100 Hz to 1 MHz, Vi = 100 mV (RMS), CL = 2.2 µF and ILDO = 10 mA.

2002 Mar 14

14

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