TFRA08C13 データシートの表示（PDF） - Agere -> LSI Corporation
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TFRA08C13 Datasheet PDF : 188 Pages
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Preliminary Data Sheet
October 2000
TFRA08C13 OCTAL T1/E1 Framer
Register Maps (continued)
Transmit Signaling Registers (Read/Write)
The address of the registers is shown with the most significant digit, designated by Y, which is used to identify each
framer (for framer 1—framer 8, Y = 2—9, respectively).
Table 185. Transmit Signaling Registers Map
Transmit
Signaling
FRM_TSR05
FRM_TSR1
FRM_TSR2
FRM_TSR3
FRM_TSR4
FRM_TSR5
FRM_TSR6
FRM_TSR7
FRM_TSR8
FRM_TSR9
FRM_TSR10
FRM_TSR11
FRM_TSR12
FRM_TSR13
FRM_TSR14
FRM_TSR15
FRM_TSR165
FRM_TSR17
FRM_TSR18
FRM_TSR19
FRM_TSR20
FRM_TSR21
FRM_TSR22
FRM_TSR23
FRM_TSR246
FRM_TSR256
FRM_TSR266
FRM_TSR276
FRM_TSR286
FRM_TSR296
FRM_TSR306
FRM_TSR316
Clear on
Read (COR)
Read (R)
Write (W)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
Bit 61 Bit 51 Bit 42 Bit 33 Bit 23 Bit 14
G_0
F_0
—
D_0
C_0
B_0
G_1
F_1
—
D_1
C_1
B_1
G_2
F_2
—
D_2
C_2
B_2
G_3
F_3
—
D_3
C_3
B_3
G_4
F_4
—
D_4
C_4
B_4
G_5
F_5
—
D_5
C_5
B_5
G_6
F_6
—
D_6
C_6
B_6
G_7
F_7
—
D_7
C_7
B_7
G_8
F_8
—
D_8
C_8
B_8
G_9
F_8
—
D_8
C_8
B_8
G_10 F_10
—
D_10 C_10 B_10
G_11 F_11
—
D_11 C_11 B_11
G_12 F_12
—
D_12 C_12 B_12
G_13 F_13
—
D_13 C_13 B_13
G_14 F_14
—
D_14 C_14 B_14
G_15 F_15
—
D_15 C_15 B_15
G_16 F_16
—
D_16 C_16 B_16
G_17 F_17
—
D_17 C_17 B_17
G_18 F_18
—
D_18 C_18 B_18
G_19 F_19
—
D_19 C_19 B_19
G_20 F_20
—
D_20 C_20 B_20
G_21 F_21
—
D_21 C_21 B_21
G_22 F_22
—
D_22 C_22 B_22
G_23 F_23
—
D_23 C_23 B_23
X7
X
—
D_24 C_24 B_24
X
X
—
D_25 C_25 B_25
X
X
—
D_26 C_26 B_26
X
X
—
D_27 C_27 B_27
X
X
—
D_28 C_28 B_28
X
X
—
D_29 C_29 B_29
X
X
—
D_30 C_30 B_30
X
X
—
D_31 C_31 B_31
Bit 0 Register Address
(hex)
Framer 1—8
A_0
A_1
A_2
A_3
A_4
A_5
A_6
A_7
A_8
A_8
A_10
A_11
A_12
A_13
A_14
A_15
A_16
A_17
A_18
A_19
A_20
A_21
A_22
A_23
A_24
A_25
A_26
A_27
A_28
A_29
A_30
A_31
YE0
YE1
YE2
YE3
YE4
YE5
YE6
YE7
YE8
YE9
YEA
YEB
YEC
YED
YEE
YEF
YF0
YF1
YF2
YF3
YF4
YF5
YF6
YF7
YF8
YF9
YFA
YFB
YFC
YFD
YFE
YFF
1. In the normal DS1 robbed-bit signaling modes, these bits define the corresponding receive channel signaling mode and are
copied into the received signaling registers. In the CEPT signaling modes, these bits are ignored.
2. These bits contain unknown data.
3. In DS1 4-state and 2-state signaling modes, these bits contain unknown data.
4. In DS1 2-state signaling mode, these bits contain unknown data.
5. In the CEPT signaling modes, the A-, B-, C-, D-, and P-bit information of these registers contains unknown data.
6. In the DS1 signaling modes, these registers contain unknown data.
7. Signifies known data.
LLuucceenntt TTeecchhnnoollooggiieess IInncc..
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