AD9857/PCB(Rev0) データシートの表示（PDF） - Analog Devices

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AD9857/PCB
(Rev.:Rev0)

CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter

Analog Devices 

AD9857

MODES OF OPERATION

The AD9857 has three operating modes:

• Quadrature Modulation Mode (Default)

• Single-Tone Mode

• Interpolating DAC Mode

Mode selection is accomplished by programming a control reg-

ister via the Serial Port. The Inverse SINC filter and output scale

multiplier are available in all three modes.

Quadrature Modulation Mode

In Quadrature Modulation Mode both the I and Q data paths

are active. A block diagram of the AD9857 operating in the

Quadrature Modulation Mode is shown in Figure 16.

In Quadrature Modulation Mode, the PDCLK/FUD pin is an

output and functions as the Parallel Data Clock (PDCLK), which

serves to synchronize the input of data to the AD9857. In this

mode, the input data must be synchronized with the rising edge

of PDCLK. The PDCLK operates at twice the rate of either the

I or Q data path. This is because of the fact that the I and Q data

must be presented to the parallel port as two 14-bit words mul-

tiplexed in time. One I word and one Q word together comprise

one internal sample. Each sample is propagated along the inter-

nal data pathway in parallel fashion.

The DDS Core provides a quadrature (sin and cos) local oscilla-

tor signal to the quadrature modulator, where the I and Q data

are multiplied by the respective phase of the carrier and summed

together, to produce a quadrature-modulated data stream.

All of this occurs in the digital domain, and only then is the digital

data stream applied to the 14-bit DAC to become the quadrature-

modulated analog output signal.

PARALLEL

DATA IN

(14-BIT)

INVERSE

I CIC FILTER

D 14

E

M

U

14

X

Q

INV

CIC

M

U

X

FIXED

INTER-

POLATOR

(4 )

PROGRAMMABLE

INTERPOLATOR

CIC

(2 – 63 )

QUADRATURE

MODULATOR

M

U

X

M

U

X

AD9857

INVERSE

SINC FILTER

INV

SINC

M

U

X 14

8

14-BIT

DAC

DDS

CORE

OUTPUT

SCALE

VALUE

CONTROL REGISTERS

TUNING

WORD 32

TIMING & CONTROL

DAC_RSET

IOUT

IOUT

POWER-

DOWN

LOGIC

PROFILE

SELECT

LOGIC

M

U

X

CLOCK

MULTIPLIER

(4 – 20 )

MODE

CONTROL

REFCLK

REFCLK

PDCLK/ TxENABLE RESET CIC

SERIAL

FUD

OVERFLOW PORT

DIGITAL

POWER-

DOWN

PS1 PS0

Figure 16. Quadrature Modulation Mode

PLL

LOCK

CLOCK

INPUT

MODE

–10–

REV. 0

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