MSM82C54-2GS データシートの表示（PDF） - Oki Electric Industry

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MSM82C54-2GS

CMOS PROGRAMMABLE INTERVAL TIMER

Oki Electric Industry 

¡ Semiconductor

MSM82C54-2RS/GS/JS

Null count indicates the count value finally written in the counter register (CR) has been

loaded in the counter element (CE). The time when the count value was loaded in the CE

depends on the mode of each counter, and it cannot be known by reading the counter value

because the count value does not tell the new count value if the counter is latched. The null

count operation is shown below.

Operation

A. Control word register writing

B. Count register (CR) writing

C. New count loading to CE (CRÆCE)

Result

Null count = 1

Null count = 1

Null count = 0

Note: The null count operation for each counter is independent. When the 2-byte count

is programmed, the null count is set to 1 when the count value of the second byte

is written.

If status latching is carried out multiple times before status reading, other than the first

status latch is ignored.

Simultaneous latching of the count and status of the selected counter is also possible. For

this purpose, set bits D4 and D3, COUNT and STATUS bits, to 00. This is functionally the

same as writing two separate read back commands at the same time. If counter/status

latching is carried out multiple times before each reading, other than the first one is ignored

here again. The example is shown below.

Command

D7 D6 D5 D4 D3 D2 D1 D0

Contents

Read back status and count

1 1 0 0 0 0 1 0 (counter 0)

Counter 0 Counter 1 Counter 2

Count Status Count Status Count Status

L

L — —— —

1 1 1 0 0 1 0 0 Read back status (counter 1)

L

1 1 1 0 1 1 0 0 Read back status (counter 1 and 2) L

1 1 0 1 1 0 0 0 Read back status (counter 2)

L

L — L——

L

—

L

(NOTE)

—

L

L— L L

L

Read back status and count

1 1 0 0 0 1 0 0 (counter 1)

1 1 1 0 0 0 1 0 Read back status (counter 0)

L

L

L

L

L

L

(NOTE)

L

L

(NOTE)

L

LL

L

Note: The latch command at this time point is ignored, and the first latch command is valid.

If both the count and status are latched, the status latched in the first counter read operation

is read. The order of count latching and status latching is irrelevant.

The count(s) of the next one or two reading operations is or are read.

Note:

There is the possibility of glitch noise in the output low level when reading out the data.

Peak voltage in typical condition (5 V, 25°C) is approximately 1V and in the worst

condition (5.5 V, –40°C) is approximately 1.4V.

19/23

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