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TMC2249A-1 データシートの表示(PDF) - Fairchild Semiconductor

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TMC2249A-1
Fairchild
Fairchild Semiconductor Fairchild
TMC2249A-1 Datasheet PDF : 18 Pages
First Prev 11 12 13 14 15 16 17 18
TMC2249A
PRODUCT SPECIFICATION
Once all of the products of the desired taps have been
summed, the result is available at the output. The user then
"pushes" a new time-data sample on to the appropriate even
or odd data register "stack" and reiterates the summation.
Note that the coefficient bank "pointers", the BDEL and
DDEL delay words, are alternately incremented and decre-
mented on successive filter passes to maintain alignment
between the incoming data samples and their respective
coefficients.
The effective filter speed is calculated by dividing the clock
rate by one-half the number of taps implemented.
Alternatively, non-symmetric FIR filters can be implemented
using the TMC2249A in a similar fashion. Here, a shift reg-
ister is used to delay the incoming data fed to the A input by
an amount equal to one-half the length of the filter (the
length of the A delay register).
As shown in Figure 5, the data is then sent to the C input,
thus "stacking" the A and C delay registers to create a single
N-tap FIR filter. The incremented delay words (ADEL-
DDEL) for all four inputs are identical. Again, the filter
throughput is equal to the clock speed divided by one-half
the number of taps implemented.
x(m)
TMC2011A
16-Stage Shift Register
A
B
x(m+0) h(0)
C
D
x(m+16) h(16)
x(m+15) h(15)
x(m+31) h(31)
S15-0
TMC2249A
Filter Output
Figure 5. Non-Symmetric 32-Tap FIR Filtering Using the
TMC2249A
Table 4. FIR Filtering Operation Sequence
Push
Push
Cycle A B C D ADEL CDEL BDEL DDEL ACC ENA ENB ENC END
1
–– – –0
0
0
0
LHHHH
2
–– – –1
1
1
1 HHHHH
3
–– – –2
2
2
2 HHHHH
4
–– – –3
3
3
3 HHHHH
5
–– – –4
4
4
4 HHHHH
6
–– – –5
5
5
5 HHHHH
7
–– – –6
6
6
6 HHHHH
8
–– – –7
7
7
7 HHHHH
9
–– – –8
8
8
8 HHHHH
10
–– – –9
9
9
9 HHHHH
11
–– – –A
A
A
A HHHHH
12
–– – –B
B
B
B HHHHH
13
–– – –C
C
C
C HHHHH
14
–– – –D
D
D
D HHHHH
15
–– – –E
E
E
E HHHHH
16
– – x(32) – F
F
F
F HHHLH
17
–– – –0
0
F
F HHHHH
18
–– – –1
1
E
E HHHHH
19
–– – –2
2
D
D HHHHH
20
–– – –3
3
C
C HHHHH
21
–– – –4
4
B
B HHHHH
Convolutional Sum
x(31)h(0)+x(30)h(1)
+x(29)h(2)+x(28)h(3)
+x(27)h(4)+x(26)h(5)
+x(25)h(6)+x(24)h(7)
+x(23)h(8)+x(22)h(9)
+x(21)h(10)+x(20)h(11)
+x(19)h(12)+x(18)h(13)
+x(17)h(14)+x(16)h(15)
+x(15)h(15)+x(14)h(14)
+x(13)h(13)+x(12)h(12)
+x(11)h(11)+x(10)h(10)
+x(9)h(9)+x(8)h(8)
+x(7)h(7)+x(6)h(6)
+x(5)h(5)+x(4)h(4)
+x(3)h(3)+x(2)h(2)
+x(1)h(1)+x(0)h(0)
+x(31)h(1)+x(32)h(0)
+x(29)h(3)+x(30)h(2)
+x(27)h(5)+x(28)h(4)
+x(25)h(7)+x(26)h(6)
+x(23)h(9)+x(24)h(8)
Resultant
Output
See Note 2
Notes:
1. If only the 16 MSBs of the result are used, the user may leave RND HIGH and SWAP low. If the 16 LSBs or all 24 bits of the
result are used, then RND should be set low.
15
2. s = (x(k)h(k) + x(k + 16)h(k))
K=0
REV. 1.0.2 7/6/00
11

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