CXD3503R データシートの表示（PDF） - Sony Semiconductor

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CXD3503R

Color Shading Correction IC for Liquid Crystal Projectors

Sony Semiconductor 

CXD3503R

Clock input (CKI: Pin 63)

The master clock input (CKI: Pin 63) of this IC supports TTL level input.

In addition, two modes can be set: a mode in which the CKI is used as is for the internal master clock (SLCK

(Pin 64): L) and a mode in which CKI is halved using the internal frequency divider (SLCK: H). In the latter

mode, all internal operation is at 1/2 clock, so "clock" in the description below refers to this 1/2 clock when

SLCK is H. Internal operation is at a frequency up to 41 MHz, so when inputting a clock faster than this to

CKI1, be sure to set SLCK to H.

DQ

selector

b

XQ

a

Internal master clock

s

(41MHz or less)

CKI

SLCK

HSYNC, VST, HST

Input a standard horizontal sync signal to the input HSYNC (Pin 60).

At this time, the input polarity is not fixed and is set by the serial data setting HSYNCPOL. In addition, make

sure the VST and HST pulses satisfy the following phase relationship. However, when not using pulse

eliminator display, HST (Pin 4) can be fixed to H level.

Normally input the VST pulse to the LCD panel for the VST input.

HSYNC

VST

HST

toVst

toHst

toDisp

Blanking portion

Video signal

toVst: VST shall rise 20 clocks or more after the front edge of HSYNC, and after the HST pulse.

toHst: The front edge of HST shall follow the rear edge of HSYNC

toDisp: There shall be 1.5H or more from the rise of VST to the start of the video signal.

The Sony timing generator ICs (CXD2464R, CXD3500R) pulses of the same name satisfy the above

conditions.

System clear pin input

Set the system clear pin (XCLR: Pin 61) to L and apply a forced reset in order to initialize the internal circuits

during power-on.

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