CXD3503R データシートの表示（PDF） - Sony Semiconductor

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CXD3503R

Color Shading Correction IC for Liquid Crystal Projectors

Sony Semiconductor 

CXD3503R

Serial Transfer Operation

Control method

The operation timing of this IC is controlled by serial data.

The control data is divided into 8-bit units. The first 8 bits are the main address, the next 8 bits are the sub

address, and the subsequent data is 8-bit data blocks.

The main address specifies which of the blocks in the table below are to be set. Data is set in the blocks

indicated by "1", so if the main address is set to "0F", the subsequent data is set in all data blocks.

In addition, the value set in the sub address sets the initial write address in the block specified by the main

address. Thereafter, the write address is incremented by +1 while SCTR is L for each 8 bits of data from the

address set by the sub address.

This makes it possible to set only the necessary data from an optional address.

The data set by serial register INIT5 to 0 is output in place of the correction data during serial transfer.

SCTR

SCLK

SDAT

M7 M6 M5 M4 M3 M2 M1 M0 S7 S6 S5 S4 S3 S2 S1 S0 D7 D6 D5 D4 D3 D2 D1 D0 D7’ D6’ D5’ D4’ D3’ D2’ D1’ D0’ D7’ D6’ D5’ D4’ D3’ D2’ D1’ D0’

main addr.

sub addr.

data

data

data

Main address table

Main address

01h

02h

04h

08h

Setting block

Correction point data 0 (SRAM0)

Correction point data 1 (SRAM1)

Correction point data 2 (SRAM2)

Timing control data

The SRAM numbers 0, 1 and 2 correspond to the DAC output DACO numbers 0, 1 and 2. The correction point

data set in the SRAM is reflected to the outputs of the corresponding numbers.

Correction point data 0, 1 and 2

Correction point data is set in the 6-bit × 208 words (16 horizontal points, 13 vertical points) SRAM. The set

correction data undergoes vertical interpolation and other arithmetic processing, and is then reflected to the

DACO0, 1 and 2 outputs, respectively. The correction point data is 6 bits, and is set in D5, 4, 3, 2, 1 and 0.

Setting to D7 and 6 is invalid.

See the figure on page 13 for the relationship between the correction point data position and the SRAM

address.

Example) When the main address is set to 04 and the sub address is set to 08, data is written from address

08 of correction point data 2 (SRAM2), then the address is automatically incremented and written to

the SRAM.

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