CXD3503R データシートの表示（PDF） - Sony Semiconductor
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CXD3503R Datasheet PDF : 19 Pages
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CXD3503R
HSOFF
This is the correction ON/OFF setting. When H, correction is on; when L, correction is off and the INIT5 to 0
data is output constantly. Normally set HSOFF to H.
HPOL
This sets the HSYNC input signal polarity. Set HPOL to H for positive polarity, and to L for negative polarity. Be
sure to set the polarity correctly in accordance with the input signal.
VSPOL
This sets the VST input signal polarity. Set VSPOL to H for positive polarity, and to L for negative polarity. Be
sure to set the polarity correctly in accordance with the input signal. The Sony timing generator ICs CXD2464R
and CXD3500R output an inverse polarity VST pulse for up/down inverse drive of a SVGA panel. Therefore,
take special care for the VST polarity when using this IC with a SVGA panel.
DWN, RGT
DWN and RGT set up/down and right/left inversion, respectively. Normal scan is supported when DWN is H
and RGT is H, and up/down and/or right/left inversion of the panel is supported by reading the correction data
set in the RAM in the reverse order when these are set to L, respectively. These settings can be controlled
from the external pins of the same name DWN (Pin 5) and RGT (Pin 6) by setting CTRL (Pin 7) to H. In this
case these serial settings are invalid.
DACKP2 to 0
This sets the DAC clock phase. Normally set to "2" to satisfy the internal DAC clock and data setup/hold
specifications.
STBY1 and 0
This is the standby setting. Standby mode results when STBY1, 0 are set to H, L. At this time, the internal
clock is supplied only to the serial interface block, and operation of all other blocks is stopped. Buffer outputs
AOUT2, 1 and 0 and digital outputs DOUT25 to 20, 15 to 10 and 05 to 00 are all high impedance at this time.
INIT5 to 0
This sets the DACO output level when correction is off. When serial data HSOFF is set to L, the data for this
setting is output regardless of the correction data set in the RAM.
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