TSA1002CF(2000) データシートの表示（PDF） - STMicroelectronics
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TSA1002CF Datasheet PDF : 19 Pages
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TSA1002
External reference
It is possible to use an external reference voltage
instead of the internal one for specific applications
requiring even better linearity or enhanced
temperature behaviour. In this case, the amplitude
of the external voltage must be at least equal to
the internal one (1.03V). Using the
STMicroelectronics Vref TS821 leads to optimum
performances when configured as shown on
Figure 8.
Figure 8 : External reference setting
1kΩ
VCCA VREFP
VIN
TSA1002
VINB
VREFM
330pF
TS821
external
reference
10nF 470nF
At 15Msps sampling frequency, 1MHz input
frequency and -1dBFS amplitude signal,
performances can be improved of up to 2dBc on
SFDR and 0.3dB on SINAD. At 50Msps sampling
frequency, 1MHz input frequency and -1dBFS
amplitude signal, performances can be improved
of up to 1dBc on SFDR and 0.6dB on SINAD.
This can be very helpful for example for
multichannel application to keep a good matching
among the sampling frequency range.
Clock input
The quality of your converter is very dependant on
your clock input accuracy, in terms of aperture
jitter; the use of low jitter crystal controlled
oscillator is recommended.
The duty cycle must be between 45% and 55%.
The clock power supplies must be separated from
the ADC output ones to avoid digital noise
modulation at the output.
It is recommended to always keep the circuit
clocked, even at the lowest specified sampling
frequency of 0.5Msps, before applying the supply
voltages.
Power consumption
The internal architecture of the TSA1002 enables
to optimize the power consumption according to
the sampling frequency of the application. For this
purpose, a resistor is placed between IPOL and
the analog Ground pins.
The TSA1002 will combine highest performances
and lowest consumption at 50Msps when Rpol is
in the range of 12kΩ to 20kΩ.
At lower sampling frequency, this value of resistor
may be changed and the consumption will
decrease as well.
The figure 9 sums up the relevant data.
Figure 9 : Analog Current consumption vs. Fs
According value of Rpol polarization resistance
60
50
40
30
20
10
0
25
RPOL
ICCA
35
45
55
65
Fs (MHz)
20
18
16
14
12
10
8
6
4
2
0
75
Layout precautions
To use the ADC circuits in the best manner at high
frequencies, some precautions have to be taken
for power supplies:
- First of all, the implementation of 4 separate
proper supplies and ground planes (analog,
digital, internal and external buffer ones) on the
PCB is mandatory for high speed circuit
applications to provide low inductance and low
resistance common return.
The separation of the analog signal from the
digital part is essential to prevent noise from
coupling onto the input signal.
- Power supply bypass capacitors must be placed
as close as possible to the IC pins in order to
improve high frequency bypassing and reduce
harmonic distortion.
- Proper termination of all inputs and outputs must
be incorporated with output termination resistors;
then the amplifier load will be only resistive and
the stability of the amplifier will be improved. All
leads must be wide and as short as possible
especially for the analog input in order to decrease
parasitic capacitance and inductance.
- To keep the capacitive loading as low as
possible at digital outputs, short lead lengths of
routing are essential to minimize currents when
the output changes. To minimize this output
15/19
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