AD9822 データシートの表示（PDF） - Analog Devices
部品番号
コンポーネント説明
メーカー
AD9822 Datasheet PDF : 20 Pages
| |||
AD9822
APPLICATIONS
CIRCUIT AND LAYOUT RECOMMENDATIONS
Figure 16 shows the recommended circuit configuration for
3-channel CDS mode operation. The recommended input
coupling capacitor value is 0.1 µF (see the Circuit Operation
section). A single ground plane is recommended for the
AD9822. A separate power supply may be used for DRVDD,
the digital driver supply, but this supply pin should still be
decoupled to the same ground plane as the rest of the AD9822.
The loading of the digital outputs should be minimized, either
by using short traces to the digital ASIC or by using external
digital buffers. To minimize the effect of digital transients
during major output code transitions, the falling edge of
CDSCLK2 should occur coincident with or before the rising
edge of ADCCLK (see Figure 3 through Figure 6 for timing).
All 0.1 µF decoupling capacitors should be located as close as
possible to the AD9822 pins. When operating in single-channel
mode, the unused analog inputs should be grounded.
Figure 17 shows the recommended circuit configuration for
3-channel SHA mode. All of the above considerations also apply
for this configuration, except that the analog input signals are
directly connected to the AD9822 without the use of coupling
capacitors. The analog input signals must already be dc-biased
between 0 V and 2 V (see the Circuit Operation section).
3
CLOCK INPUTS
5V/3V
0.1µF
8
DATA OUTPUTS
5V
1 CDSCLK1
AVDD 28
2 CDSCLK2
AVSS 27
3 ADCCLK
VINR 26
4 OEB
OFFSET 25
5 DRVDD
VING 24
AD9822
6 DRVSS
CML 23
7 D7 (MSB)
VINB 22
8 D6
CAPT 21
9 D5
CAPB 20
10 D4
AVSS 19
11 D3
AVDD 18
12 D2
SLOAD 17
13 D1
SCLK 16
14 D0 (LSB)
SDATA 15
0.1µF
3
0.1µF
0.1µF
0.1µF
RED INPUT
GREEN INPUT
BLUE INPUT
0.1µF
0.1µF
1.0µF
0.1µF
+
0.1µF
10µF 0.1µF
0.1µF
5V
SERIAL INTERFACE
Figure 16. Recommended Circuit Configuration, 3-Channel CDS Mode
3
CLOCK INPUTS
5V/3V
0.1µF
8
DATA OUTPUTS
5V
RED INPUT
1 CDSCLK1
AVDD 28
2 CDSCLK2
AVSS 27
3 ADCCLK
VINR 26
4 OEB
OFFSET 25
5 DRVDD
VING 24
AD9822
6 DRVSS
CML 23
7 D7 (MSB)
VINB 22
8 D6
CAPT 21
9 D5
CAPB 20
10 D4
AVSS 19
11 D3
AVDD 18
12 D2
SLOAD 17
13 D1
SCLK 16
14 D0 (LSB)
SDATA 15
0.1µF
GREEN INPUT
BLUE INPUT
0.1µF
0.1µF
+
0.1µF
10µF 0.1µF
0.1µF
5V
3
SERIAL INTERFACE
Figure 17. Recommended Circuit Configuration, 3-Channel SHA Mode (Analog Inputs Sampled with Respect to Ground)
Rev. B | Page 17 of 20
Share Link: 