UPB1009K
As illustrated in the operation timing chart below, the data of SampleN is pipeline delayed by 1.5 clocks during
normal operation, and is output at the rising edge of the sample clock with output delay time Tod. When the
operation is changed from normal operation to power-down operation, the status of the output data
immediately before the power-down operation is retained (drive status).
The following table shows each timing parameter for reference purposes.
Symbol
Parameter
Tod Output Delay
Tpld Pipeline Delay
Tds Sampling Delay
(Aperture Delay)
Toh Output Hold Time
Test Conditions
CL = 10 pF, fclk = 19.2 MHz
MIN.
−
−
−
TYP.
−
1.5
2
MAX.
12
−
−
Unit
ns
clock
ns
2
−
−
ns
15