UPD16432BGC-001-9EU データシートの表示（PDF） - NEC => Renesas Technology
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UPD16432BGC-001-9EU Datasheet PDF : 36 Pages
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µPD16432B
SWITCHING SPECIFICATIONS
(UNLESS SPECIFIED OTHERWISE, TA = –40 to +85°C, VDD = VLCD = 5 V ±10%, RL = 5 kΩ, CL = 150 pF)
Parameter
Oscillator frequency
Output data delay time
Output data delay time
SYNC delay time
Symbol
fOSC
tPZL
tPLZ
tDSYNC
Test Conditions
R = 100 kΩ
SCK ↓ → DATA ↓
SCK ↓ → DATA ↑
MIN. TYP. MAX. Unit
175
250
325
kHz
100
ns
300
ns
1.5
µs
Note The time for one frame is found as follows.
1 frame = 1/fOSC × 128 clocks × duty number + 1/fOSC × 64 clocks
If fOSC = 250 kHz and duty = 1/15, 1 frame = 4 µs × 128 × 15 + 4 µs × 64 = 7.94 ms
REQUIRED TIMING CONDITIONS
(UNLESS SPECIFIED OTHERWISE, TA = –40 to +85°C, VDD = 5 V ±10%, VLCD = 8 V ±10%, RL = 5 kΩ,
CL = 150 pF)
Parameter
Clock frequency
High-level clock pulse width
Low-level clock pulse width
Shift-clock cycle
High-level shift clock pulse width
Low-level shift clock pulse width
Shift clock hold time
Data setup time
Data hold time
STB hold time
STB hold time
Wait time
SYNC removal time
Standby transition time
Reset pulse width
Power-ON reset time
Symbol
fOSC
tWHC
tWLC
tCYK
tWHK
tWLK
tHSTBK
tDS
tDH
tHKSTB
tWSTB
tWAIT
tSREM
tPSTB
tWRS
tPON
Test Conditions
OSCIN external clock
OSCIN external clock
OSCIN external clock
SCK
SCK
SCK
STB ↑ → SCK ↓
DATA → SCK ↑
SCK ↑ → DATA
SCK ↑ → STB ↓
8th SCK ↑ → 9th SCK ↓, in data read
RESET
From Power-ON
MIN. TYP. MAX. Unit
100
500
kHz
1
5
µs
1
5
µs
900
ns
400
ns
400
ns
1.5
µs
100
ns
200
ns
1
µs
1
µs
1
µs
250
ns
10
µs
0.1
µs
4
CLK
19
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