UPD16634A データシートの表示（PDF） - NEC => Renesas Technology
部品番号
コンポーネント説明
メーカー
UPD16634A Datasheet PDF : 20 Pages
| |||
µPD16634A
Electrical Characteristics (TA = –10 to +75 °C, VDD1 = 3.3 V ± 0.3 V, VDD2 = 8.0 V ± 0.5 V, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Input leakage current
IIL
±1.0
µA
High-level output voltage
VOH
STHR(STHL),IO=0 mA
VDD1−0.1
V
Low-level output voltage
VOL
STHR(STHL),IO=0 mA
0.1
V
γ -corrected supply current
Iγ
V0−V9 = 8 V
V0,V9
0.3
0.6
mA
Driver output current
IVOH
VX=7 V, VOUT=1 VNote1
−0.5
mA
IVOL
VX=1 V, VOUT=7 VNote1
0.5
mA
Output voltage deviationNote2
∆VO
Input data : 00H to 3FH
±5
±20
mV
Average output voltage variationNote3 ∆VAV
Input data : 00H to 3FH
±10
mV
Output voltage range
VO
Input data : 00H to 3FH
0.1
VDD2−0.1
V
Logic part dynamic current
consumptionNotes4,5
IDD1
VDD1, when with no load
0.5
3.5
mA
5 Driver part dynamic current
consumptionNotes4,5
IDD2
VDD2, when with no load
2.2
8.0
mA
Notes 1. VX refers to the output voltage of analog output pins S1 to S300.
VOUT refers to the voltage applied to analog output pins S1 to S300.
2. The output voltage deviation refers to the voltage difference between adjoining output pins when the
display data is the same (within the chip).
3. The average output voltage variation refers to the average output voltage difference between chips. The
average output voltage refers to the average voltage between chips when the display data is the same.
4. The STB cycle is defined to be 20 µs at fCLK = 40 MHz. The TYP. values refer to an all black or all white
input pattern. The MAX. value refers to the measured values in the dot checkerboard input pattern.
5. Refers to the current consumption per driver when cascades are connected under the assumption of
SVGA single-sided mounting (10 units).
Switching Characteristics (TA = −10 to +75 °C, VDD1 = 3.3 V ± 0.3 V, VDD2 = 8.0 V ± 0.5 V, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Start pulse delay time
Driver output delay time
tPLH1
tPHL2
tPHL3
tPLH2
tPLH3
CL = 25 pF
CL = 125 pF, RL = 4 kΩNote
13
20
ns
3.7
8
µs
5.3
14
µs
3.0
8
µs
5.3
14
µs
Input capacitance
C1
STHR,STHL excluded, TA = 25 °C
5.4
15
pF
C2
7.6
15
pF
Note Load condition
output
RL
RL
RL
RL
RL = 1kΩ
CL = 25pF
CL
CL
CL
CL
CL
Data Sheet S12595EJ2V0DS00
13
Share Link: 