UPD16750 データシートの表示（PDF） - NEC => Renesas Technology
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UPD16750 Datasheet PDF : 24 Pages
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µPD16750
Timing Requirements (TA = –10 to +75°C, VDD1 = 3.3 V ± 0.3 V, VSS1 = 0 V, tr = tf = 8.0 ns)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Clock Pulse Width
PWCLK
25
Clock Pulse High Period
PWCLK(H)
4
Clock Pulse Low Period
PWCLK(L)
4
Data Setup Time
tSETUP1
2
Data Hold Time
tHOLD1
2
Start Pulse Setup Time
tSETUP2
2
Start Pulse Hold Time
tHOLD2
2
• POL21/22 Setup Time
tSETUP3
2
• POL21/22 Hold Time
tHOLD3
2
Start Pulse Low Period
tSPL
1
STB Pulse Width
PWSTB
2
Data Invalid Period
tINV
1
Last Data Timing
tLDT
2
CLK-STB Time
tCLK-STB CLK ↑ → STB ↑
6
STB-CLK Time
tSTB-CLK STB ↑ → CLK ↑
6
Time Between STB and Start Pulse
tSTB-STH STB ↑ → STHR(STHL) ↑
2
POL-STB Time
tPOL-STB POL ↑ or ↓ → STB ↑
–5
STB-POL Time
tSTB-POL STB ↓ → POL ↓ or ↑
6
Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
µs
CLK
CLK
ns
ns
CLK
ns
ns
Data Sheet S13719EJ4V0DS00
19
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