UPD703003A データシートの表示（PDF） - NEC => Renesas Technology
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UPD703003A Datasheet PDF : 40 Pages
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µPD703003A, 703004A, 703025A
(1) Clock timing
Parameter
Symbol
Conditions
X1 input cycle
X1 input high-level width
X1 input low-level width
X1 input rise time
<1> tCYX
<2> tWXH
<3> tWXL
<4> tXR
Direct mode
PLL mode (PLL locked)
Direct mode
PLL mode
Direct mode
PLL mode
Direct mode
PLL mode
X1 input fall time
<5> tXF
CPU operating frequency
–φ
CLKOUT output cycle
<6> tCYK
CLKOUT input high-level width <7> tWKH
CLKOUT input low-level width <8> tWKL
CLKOUT input rise time
<9> tKR
CLKOUT input fall time
<10> tKF
Delay time from X1↓ to CLKOUT <11> tDXK
Direct mode
PLL mode
Direct mode
Notes 1. When using A/D converter: 100 ns
When not using A/D converter: 250 ns
2. When using A/D converter: 5 MHz
When not using A/D converter: 2 MHz
3. When using A/D converter: 200 ns
When not using A/D converter: 500 ns
Remark T = tCYK
25 MHz Version 33 MHz Version Unit
MIN. MAX. MIN. MAX.
20 Note 1 15 Note 1 ns
200 Note 1 151 Note 1 ns
7
6
ns
80
60
ns
7
6
ns
80
60
ns
7
7
ns
15
10
ns
7
7
15
10
Note 2 25 Note 2 33
40 Note 3 30 Note 3
0.5T – 5
0.5T – 5
0.5T – 5
0.5T – 5
5
5
5
5
3
17
3
17
ns
ns
MHz
ns
ns
ns
ns
ns
ns
X1 (input)
<1>
<2>
<3>
CLKOUT (output)
<11>
<4>
<5>
<11>
<6>
<7>
<8>
<9>
<10>
Data Sheet U13188EJ4V0DS00
21
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