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UPD750008CUA データシートの表示(PDF) - NEC => Renesas Technology

部品番号
コンポーネント説明
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UPD750008CUA
NEC
NEC => Renesas Technology NEC
UPD750008CUA Datasheet PDF : 84 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)
Address 7 6 5
0 0 0 0 H MBE RBE 0
Fig. 5-2 Program Memory Map (in µPD750006)
Internal reset start address
0
(high-order 5 bits)
0 0 0 2 H MBE RBE 0
Internal reset start address
INTBT/INT4 start address
(low-order 8 bits)
(high-order 5 bits)
0 0 0 4 H MBE RBE 0
INTBT/INT4
INT0
0 0 0 6 H MBE RBE 0
INT0
INT1
0 0 0 8 H MBE RBE 0
INT1
INTCSI
0 0 0 A H MBE RBE 0
INTCSI
INTT0
0 0 0 C H MBE RBE 0
INTT0
INTT1
start address
start address
start address
start address
start address
start address
start address
start address
start address
start address
(low-order 8 bits)
(high-order 5 bits)
(low-order 8 bits)
(high-order 5 bits)
(low-order 8 bits)
(high-order 5 bits)
(low-order 8 bits)
(high-order 5 bits)
(low-order 8 bits)
CALLF
!faddr
instruction
entry
address
Branch address
of BR BCXA, BR
BCDE, BR !addr,
BRA !addr1Note or
CALLA !addr1Note
instruction
CALL !addr
instruction
subroutine entry
address
BR $addr
instruction relative
branch address
-15 to -1,
+2 to +16
(high-order 5 bits)
INTT1
start address
(low-order 8 bits)
BRCB !caddr
instruction
branch
address
0020H
007FH
0080H
07FFH
0800H
GETI instruction reference table
Branch destination
address and
subroutine entry
address when GETI
instruction is executed
0FFFH
1000H
17FFH
BRCB !caddr
instruction
branch
address
Note Can be used only in the Mk ΙΙ mode.
Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address with
only the 8 low-order bits of the PC changed.
18

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