UPD75008 データシートの表示（PDF） - NEC => Renesas Technology

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UPD75008

4-BIT SINGLE-CHIP MICROCOMPUTER

NEC => Renesas Technology 

µPD75004, 75006, 75008

LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE

(Ta = –40 to +85°C)

Parameter

Symbol

Conditions

MIN. TYP. MAX. Unit

Data Retention Supply

Voltage

VDDDR

2.0

6.0

V

Data Retention Supply

Current*1

IDDDR

Release Signal Set Time tSREL

Oscillation Stabilization tWAIT

Wait Time*2

VDDDR = 2.0 V

Released by RESET

Released by interrupt request

0.1

10

µA

0

µs

217/fX

ms

*3

ms

*1: Does not include current flowing through internal pull-up resistor

2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent

unstable operation when oscillation is started.

3: Depends on the setting of the basic interval timer mode register (BTM) as follows:

BTM3

–

–

–

–

BTM2

0

0

1

1

BTM1

0

1

0

1

BTM0

0

1

1

1

WAIT time ( ): fXX = 4.19 MHz

220/fXX (approx. 250 ms)

217/fXX (approx. 31.3 ms)

215/fXX (approx. 7.82 ms)

213/fXX (approx. 1.95 ms)

DATA RETENTION TIMING (releasing STOP mode by RESET)

STOP mode

Data retention mode

Internal reset operation

HALT mode

Operation

mode

VDD

RESET

STOP instruction

execution

VDDDR

tSREL

tWAIT

DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt)

STOP mode

Data retention mode

HALT mode

Operation

mode

VDD

VDDDR

STOP instruction execution

tSREL

Standby release signal

(interrupt request)

tWAIT

52

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