UPD750064A データシートの表示（PDF） - NEC => Renesas Technology

部品番号

コンポーネント説明

メーカー

UPD750064A

4 BIT SINGLE CHIP CMOS MICROCOMPUTERS

NEC => Renesas Technology 

µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)

4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE

4.1 Differences between Mk I Mode and Mk II Mode

The CPU of the µPD750068 has the following two modes: Mk I and Mk II, either of which can be selected.

The mode can be switched by the bit 3 of the stack bank select register (SBS).

• Mk I mode: Upward compatible with µPD75068. Can be used in the 75XL CPU with a ROM capacity

of up to 16 Kbytes.

• Mk II mode: Incompatible with µPD75068. Can be used in all the 75XL CPUs including those products

whose ROM capacity is more than 16 Kbytes.

Table 4-1. Differences between Mk I Mode and Mk II Mode

Number of stack bytes

for subroutine instructions

BRA !addr1 instruction

CALLA !addr1 instruction

CALL !addr instruction

CALLF !faddr instruction

2 bytes

Mk I Mode

Not available

3 machine cycles

2 machine cycles

Mk II Mode

3 bytes

Available

4 machine cycles

3 machine cycles

Caution

The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and

75XL Series. Therefore, this mode is effective for enhancing software compatibility

with products exceeding 16 Kbytes.

When the Mk II mode is selected, the number of stack bytes used during

execution of subroutine call instructions increases by one byte per stack

compared to the Mk I mode. When the CALL !addr and CALLF !faddr instructions

are used, the machine cycle becomes longer by one machine cycle. Therefore,

use the Mk I mode if the RAM efficiency and processing performance are more

important than software compatibility.

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Data Sheet U10165EJ2V0DS00

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