UPD750068A データシートの表示（PDF） - NEC => Renesas Technology

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UPD750068A

4 BIT SINGLE CHIP CMOS MICROCOMPUTERS

NEC => Renesas Technology 

µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)

Figure 5-1. Program Memory Map (µPD750064)

Address 7 6 5

0 0 0 H MBE RBE 0

0 0 2 H MBE RBE 0

0 0 4 H MBE RBE 0

0 0 6 H MBE RBE 0

0 0 8 H MBE RBE 0

0 0 A H MBE RBE 0

0 0 C H MBE RBE 0

4

0 Internal reset start address

Internal reset start address

0 INTBT/INT4 start address

INTBT/INT4 start address

0 INT0

start address

INT0

start address

0 INT1

start address

INT1

start address

0 INTCSI

start address

INTCSI

start address

0 INTT0

start address

INTT0

start address

0 INTT1

start address

INTT1

start address

0

(high-order 4 bits)

(low-order 8 bits)

(high-order 4 bits)

(low-order 8 bits)

(high-order 4 bits)

(low-order 8 bits)

(high-order 4 bits)

(low-order 8 bits)

(high-order 4 bits)

CALLF

! faddr

instruction

entry

address

Branch address

of BR BCXA, BR

BCDE, BR !addr,

BRA !addr1Note or

CALLA !addr1Note

instruction

(low-order 8 bits)

(high-order 4 bits)

CALL !addr

instruction

subroutine entry

address

(low-order 8 bits)

(high-order 4 bits)

(low-order 8 bits)

BR $addr

instruction relative

branch address

–15 to –1,

+2 to +16

020H

07FH

080H

7FFH

800H

GETI instruction reference table

BRCB

!caddr

instruction

branch

address

Branch destination

address and

subroutine entry

address when

GETI instruction

is executed

FFFH

Note Can be used only in the Mk II mode.

Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order

eight bits of PC by executing the BR PCDE or BR PCXA instruction.

Data Sheet U10165EJ2V0DS00

19

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