UPD750068CUA データシートの表示（PDF） - NEC => Renesas Technology

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UPD750068CUA

4 BIT SINGLE CHIP CMOS MICROCOMPUTERS

NEC => Renesas Technology 

µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)

Address 7 6 5

0 0 0 0 H MBE RBE 0

Figure 5-2. Program Memory Map (µPD750066)

Internal reset start address

0

(high-order 5 bits)

Internal reset start address

(low-order 8 bits)

0 0 0 2 H MBE RBE 0 INTBT/INT4 start address

(high-order 5 bits)

INTBT/INT4 start address

(low-order 8 bits)

0 0 0 4 H MBE RBE 0 INT0

0 0 0 6 H MBE RBE 0

INT0

INT1

0 0 0 8 H MBE RBE 0

INT1

INTCSI

0 0 0 A H MBE RBE 0

INTCSI

INTT0

0 0 0 C H MBE RBE 0

INTT0

INTT1

start address

start address

start address

start address

start address

start address

start address

start address

start address

(high-order 5 bits)

(low-order 8 bits)

(high-order 5 bits)

(low-order 8 bits)

(high-order 5 bits)

(low-order 8 bits)

(high-order 5 bits)

(low-order 8 bits)

CALLF

! faddr

instruction

entry

address

Branch address

of BR BCXA, BR

BCDE, BR ! addr,

BRA ! addr1Note or

CALLA ! addr1Note

instruction

CALL ! addr

instruction

subroutine entry

address

BR $ addr

instruction relative

branch address

–15 to –1,

+2 to +16

(high-order 5 bits)

INTT1

start address

(low-order 8 bits)

BRCB ! caddr

instruction

branch

address

0020H

007FH

0080H

07FFH

0800H

GETI instruction reference table

Branch destination

address and

subroutine entry

address when GETI

instruction is executed

0FFFH

1000H

17FFH

BRCB ! caddr

instruction

branch

address

Note Can be used only in the Mk II mode.

Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order

eight bits of PC by executing the BR PCDE or BR PCXA instruction.

20

Data Sheet U10165EJ2V0DS00

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