UPD750066GTA データシートの表示（PDF） - NEC => Renesas Technology

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UPD750066GTA

4 BIT SINGLE CHIP CMOS MICROCOMPUTERS

NEC => Renesas Technology 

µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)

Figure 6-6. Timer/Event Counter Block Diagram (Channel 0)

8

TM0

– TM06 TM05 TM04 TM03 TM02 TM01 TM00

PORT1. 3

Decoder

Internal bus

8

TMOD0

Modulo register (8)

8

Input

buffer

TI0/P13

Watch timer (INTW) output

fX/22

From clock

generator

fX/24

fX/26

fX/28

fX/210

MPX

Comparator (8)

8

T0

CP Count register (8)

Clear

16-bit

timer/event

counter mode

Timer

operation

start

Timer/event counter (channel 1) TM12 signal

(When 16-bit timer/event counter mode)

TOE0 PORT2.0 PMGB bit 2

TO

P20

enable output

flag

latch

Port 2

input/

output

mode

Match TOUT

F/F

Reset TOUT0

Output

buffer

Overflow

P20/PTO0

To serial

interface

Timer/event

counter

(channel 1)

clock input

INTT0

(IRQT0

set signal)

IRQT0

clear signal

RESET

Timer/event counter (channel 1) match signal

(When 16-bit timer/event counter mode)

Timer/event counter (channel 1) clear signal

(When 16-bit timer/event counter mode)

30

Data Sheet U10165EJ2V0DS00

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