UPD750064(A) データシートの表示（PDF） - NEC => Renesas Technology

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UPD750064(A)

4 BIT SINGLE CHIP CMOS MICROCOMPUTERS

NEC => Renesas Technology 

µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)

Figure 6-7. Timer/Event Counter Block Diagram (Channel 1)

8

TM1

– TM16 TM15 TM14 TM13 TM12 TM11 TM10

PORT1.2

Decoder

Input

buffer

TI1/P12/INT2

Timer/event counter output

(channel 0)

fX/22

fX/26

From clock

generator

fX/28

fX/210

fX/212

MPX

Internal bus

8

TMOD1

TOE1

PORT2.1 PMGB bit 2

TO

enable flag

P21

output latch

Port 2

input/output

mode

Modulo register (8)

8

Comparator (8)

Match TOUT

F/F

8

T1

Reset

Output

buffer

P21/PTO1

CP Count register (8)

Clear

Timer operation start

16 bit timer/event

counter mode

Selector

RESET

IRQT1

clear signal

Timer/event counter (channel 0) TM02 signal

(When 16-bit timer/event counter mode)

Timer/event counter (channel 0) match signal/operation start

(When 16-bit timer/event counter mode)

Timer/event counter (channel 0) comparator

(When 16-bit timer/event counter mode)

INTT1

IRQT1

set signal

Data Sheet U10165EJ2V0DS00

31

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