UPD75036CW データシートの表示（PDF） - NEC => Renesas Technology
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UPD75036CW Datasheet PDF : 58 Pages
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µPD75036
5. PERIPHERAL HARDWARE FUNCTIONS
5.1 PORTS
The µPD75036 has the following three types of I/O port:
• 12 CMOS input ports (Ports 0, 1, and 11)
• 24 CMOS I/O ports (Ports 2, 3, 6, 7, 8, and 9)
• 12 N-ch open-drain I/O ports (Ports 4, 5, and 10)
Total: 48 ports
Table 5-1 Functions of Ports
Port (symbol) Function
PORT0
PORT1
4-bit input
Operation and feature
Allows input and test at any time regardless of the operation
modes of dual function pins.
PORT3Note
PORT6
PORT2
PORT7
4-bit I/O
Allows input or output mode setting in units of one bit.
Allows input or output mode setting in units of four bits.
Ports 6 and 7 make a pair, allowing data I/O in units of
eight bits.
PORT4Note
PORT5Note
PORT10Note
4-bit I/O
(N-ch
open-drain,
withstand
voltage:
10 V)
Allows input or output mode setting in units of four bits.
Ports 4 and 5 make a pair, allowing data I/O in units of
eight bits.
PORT8
PORT9
PORT11
4-bit I/O
Allows input or output mode setting in units of four bits.
4-bit input Port for 4-bit input
Note Ports 3, 4, 5 and 10 can directly drive an LED.
Remarks
Also used as SO/SB0, SI/
SB1, SCK, INT0-INT2, INT4,
and TI0 pins.
Port 6 is also used as KR0-
KR3 pins.
Port 2 is also used as PTO0,
PPO, PCL, and BUZ pins.
Also used as KR4-KR7 pins.
Use of an internal pull-up
registor can be mask-
programmed in units of one
bit.
Port 10 is also used as
MAR, MAI, MAZ, and MAT
pins.
Port 11 is also used as AN0-
AN3 pins.
5.2 CLOCK GENERATOR
Operation of the clock generator is specified by the processor clock control register (PCC) and system clock control
register (SCC).
The main system clock or subsystem clock can be selected.
The instruction execution time is variable.
• 0.95 µs, 1.91 µs, 15.3 µs (main system clock: 4.19 MHz)
• 122 µs (subsystem clock: 32.768 kHz)
17
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