UPD75048CW データシートの表示（PDF） - NEC => Renesas Technology
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UPD75048CW Datasheet PDF : 68 Pages
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µPD75048
SBI MODE (SCK: internal clock output (master))
Parameter
Symbol
Conditions
MIN.
SCK Cycle Time
tKCY3
VDD = 4.5 to 6.0 V
1600
3800
SCK High-, Low-Level tKL3
Widths
tKH3
VDD = 4.5 to 6.0 V
tKCY3/2-50
tKCY3/2-150
SB0, 1 Set-Up Time
tSIK3
150
(vs. SCK ↑ )
SB0, 1 Hold Time
tKSI3
(vs. SCK ↑ )
tKCY3/2
SCK ↓→ SB0, 1 Output tKSO3
RL = 1kΩ, CL = 100pF* VDD = 4.5 to 6.0V
0
Delay Time
0
SCK ↑→ SB0, 1 ↓
tKSB
tKCY3
SB0,1 ↓→ SCK
tSBK
tKCY3
SB0, 1 Low-Level Width tSBL
tKCY3
SB0, 1 High-Level Width tSBH
tKCY3
TYP.
MAX.
250
1000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SBI MODE (SCK: external clock input (slave))
Parameter
Symbol
Conditions
MIN. TYP. MAX.
SCK Cycle Time
tKCY4
VDD = 4.5 to 6.0 V
800
3200
SCK Ligh-, Low-Level
tKL4
Widths
tKH4
VDD = 4.5 to 6.0 V
400
1600
SB0, 1 Set-Up Time
tSIK4
100
(vs. SCK ↑ )
SB0, 1 Hold Time
tKSI4
(vs. SCK ↑ )
tKCY4/2
SCK ↓→ SB0, 1 Output
Delay Time
tKSO4
RL = 1kΩ, CL = 100pF* VDD = 4.5 to 6.0V
0
0
300
1000
SCK ↑→ SB0, 1 ↓
tKSB
tKCY4
SB0,1 ↓→ SCK ↓
tSBK
tKCY4
SB0, 1 Low-Level Width tSBL
tKCY4
SB0, 1 High-Level Width tSBH
tKCY4
*: RL and CL are load resistance and load capacitance of the SB0 and SB1 output lines.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
52
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