UPD75064CU データシートの表示（PDF） - NEC => Renesas Technology

部品番号

コンポーネント説明

メーカー

UPD75064CU

4-BIT SINGLE-CHIP MICROCOMPUTER

NEC => Renesas Technology 

µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)

4. MEMORY CONFIGURATION

• Program memory (ROM) ..... 4096 × 8 bits (0000H to 0FFFH) : µPD75064

..... 6016 × 8 bits (0000H to 177FH) : µPD75066

..... 8064 × 8 bits (0000H to 1F7FH) : µPD75068

• 0000H to 0001H : Vector table in which the program start address by reset is stored

• 0002H to 000BH : Vector table in which the program start address by interrupt is stored

• 0020H to 007FH : Table area to be referenced by GETI instruction

• Data memory

• Data area

..... 512 × 4 bits (000H to 1FFH)

• Peripheral hardware area ..... 128 × 4 bits (F80H to FFFH)

Figure 4-1. Program Memory Map

Address

765 4

0000H MBE 0 0 0

0002H MBE 0 0 0

0004H MBE 0 0 0

0006H MBE 0 0 0

0008H MBE 0 0 0

000AH MBE 0 0 0

(a) µPD75064

0

Internal reset start address (high-order 4 bits)

Internal reset start address (low-order 8 bits)

INTBT/INT4 start address (high-order 4 bits)

INTBT/INT4 start address (low-order 8 bits)

INT0 start address

INT0 start address

INT1 start address

INT1 start address

(high-order 4 bits)

(low-order 8 bits)

(high-order 4 bits)

(low-order 8 bits)

CALLF

! faddr

instruction

entry

address

INTCSI start address

(high-order 4 bits)

INTCSI start address

(low-order 8 bits)

INTT0 start address

(high-order 4 bits)

INTT0 start address

(low-order 8 bits)

CALL ! addr

instruction

subroutine entry

address

BR $addr

instruction

relative branch

address

(–15 to –1,

+2 to +16)

0020H

007FH

0080H

07FFH

0800H

GETI instruction reference table

BRCB

! caddr

instruction

branch

address

Branch destination

address specified

by GETI instruction,

Subroutine entry

address

0FFFH

14

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