UPD75064A データシートの表示（PDF） - NEC => Renesas Technology

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UPD75064A

4-BIT SINGLE-CHIP MICROCOMPUTER

NEC => Renesas Technology 

µPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)

8. RESET OPERATION

When the RESET signal is input, the µPD75068 is reset and all hardware is initialized as indicated in Table

8-1. Figure 8-1 shows the reset operation timing.

Figure 8-1. Reset Operation by RESET Input

Wait

(Approx. 31.3 ms/4.19 MHz)

RESET input

Operation mode or

standby mode

HALT mode

Operation mode

Internal reset operation

Table 8-1. Status of All Hardware after Reset (1/2)

Hardware

RESET input in standby mode

RESET input during operation

Program counter (PC)

µPD75064

Contents of lower 4 bits of address 0000H

in program memory are set to PC11 - 8,

and that of 0001H are set to PC7 - 0.

Same operation as that in

standby state

µPD75066

µPD75068

Contents of lower 5 bits of address 0000H

in program memory are set to PC12 - 8,

and that of 0001H are set to PC7 - 0.

Same operation as that in

standby state

PSW

Carry flag (CY)

Retained

Undefined

Skip flag (SK0-2)

0

0

Interrupt status flag (IST0)

0

0

Bank enable flag (MBE)

The contents of bit 7 of address 0000H

of the program memory is set to MBE.

Same operation as that in

standby state

Stack pointer (SP)

Undefined

Undefined

Data memory (RAM)

RetainedNote

Undefined

General purpose register

(X, A, H, L, D, E, B, C)

Retained

Undefined

Bank selection register (MBS)

0

0

Basic interval Counter (BT)

timer

Mode register (BTM)

Undefined

0

Undefined

0

Timer/event Counter (T0)

0

0

counter

Modulo register (TMOD0)

FFH

FFH

Mode register (TM0)

0

0

TOE0, TOUT F/F

0, 0

0, 0

Watch timer Mode register (WM)

0

0

Note Data of address 0F8H to 0FDH of the data memory becomes undefined when the RESET signal is input.

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